Changeset 904b1bc in mainline for uspace/drv/nic/rtl8139/defs.h
- Timestamp:
- 2018-05-22T10:36:58Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- a4eb3ba2
- Parents:
- 4f8772d4
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-21 17:36:30)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-22 10:36:58)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/nic/rtl8139/defs.h
r4f8772d4 r904b1bc 280 280 /** Receiver control register values */ 281 281 enum rtl8139_rcr { 282 RCR_ERTH_SHIFT = 24, /**< Early Rx treshold part shift */ 283 RCR_ERTH_SIZE = 4, /**< Early Rx treshold part size */ 284 285 RCR_MulERINT = 1 << 17, /**< Multiple early interrupt select */ 286 287 /** Minimal error frame length (1 = 8B, 0 = 64B). If AER/AR is set, RER8 288 * is "Don't care" 282 /** Early Rx treshold part shift */ 283 RCR_ERTH_SHIFT = 24, 284 /** Early Rx treshold part size */ 285 RCR_ERTH_SIZE = 4, 286 287 /** Multiple early interrupt select */ 288 RCR_MulERINT = 1 << 17, 289 290 /** Minimal error frame length (1 = 8B, 0 = 64B). 291 * If AER/AR is set, RER8 is "Don't care" 289 292 */ 290 293 RCR_RER8 = 1 << 16, 291 294 292 RCR_RXFTH_SHIFT = 13, /**< Rx FIFO treshold part shitf */ 293 RCR_RXFTH_SIZE = 3, /**< Rx FIFO treshold part size */ 294 295 RCR_RBLEN_SHIFT = 11, /**< Rx buffer length part shift */ 296 RCR_RBLEN_SIZE = 2, /**< Rx buffer length part size */ 297 298 RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, /**< 8K + 16 byte rx buffer */ 299 RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, /**< 16K + 16 byte rx buffer */ 300 RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, /**< 32K + 16 byte rx buffer */ 301 RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, /**< 64K + 16 byte rx buffer */ 302 303 RCR_MXDMA_SHIFT = 8, /**< Max DMA Burst Size part shift */ 304 RCR_MXDMA_SIZE = 3, /**< Max DMA Burst Size part size */ 305 306 RCR_WRAP = 1 << 7, /**< Rx buffer wrapped */ 307 RCR_ACCEPT_ERROR = 1 << 5, /**< Accept error frame */ 308 RCR_ACCEPT_RUNT = 1 << 4, /**< Accept Runt (8-64 bytes) frames */ 309 RCR_ACCEPT_BROADCAST = 1 << 3, /**< Accept broadcast */ 310 RCR_ACCEPT_MULTICAST = 1 << 2, /**< Accept multicast */ 311 RCR_ACCEPT_PHYS_MATCH = 1 << 1, /**< Accept device MAC address match */ 312 RCR_ACCEPT_ALL_PHYS = 1 << 0, /**< Accept all frames with 313 * phys. desticnation 314 */ 315 RCR_ACCEPT_MASK = (1 << 6) - 1 /**< Mask of accept part */ 295 /** Rx FIFO treshold part shift */ 296 RCR_RXFTH_SHIFT = 13, 297 /** Rx FIFO treshold part size */ 298 RCR_RXFTH_SIZE = 3, 299 300 /** Rx buffer length part shift */ 301 RCR_RBLEN_SHIFT = 11, 302 /** Rx buffer length part size */ 303 RCR_RBLEN_SIZE = 2, 304 305 /** 8K + 16 byte rx buffer */ 306 RCR_RBLEN_8k = 0x00 << RCR_RBLEN_SHIFT, 307 /** 16K + 16 byte rx buffer */ 308 RCR_RBLEN_16k = 0x01 << RCR_RBLEN_SHIFT, 309 /** 32K + 16 byte rx buffer */ 310 RCR_RBLEN_32k = 0x02 << RCR_RBLEN_SHIFT, 311 /** 64K + 16 byte rx buffer */ 312 RCR_RBLEN_64k = 0x03 << RCR_RBLEN_SHIFT, 313 314 /** Max DMA Burst Size part shift */ 315 RCR_MXDMA_SHIFT = 8, 316 /** Max DMA Burst Size part size */ 317 RCR_MXDMA_SIZE = 3, 318 319 /** Rx buffer wrapped */ 320 RCR_WRAP = 1 << 7, 321 /** Accept error frame */ 322 RCR_ACCEPT_ERROR = 1 << 5, 323 /** Accept Runt (8-64 bytes) frames */ 324 RCR_ACCEPT_RUNT = 1 << 4, 325 /** Accept broadcast */ 326 RCR_ACCEPT_BROADCAST = 1 << 3, 327 /** Accept multicast */ 328 RCR_ACCEPT_MULTICAST = 1 << 2, 329 /** Accept device MAC address match */ 330 RCR_ACCEPT_PHYS_MATCH = 1 << 1, 331 /** Accept all frames with phys. destination */ 332 RCR_ACCEPT_ALL_PHYS = 1 << 0, 333 /** Mask of accept part */ 334 RCR_ACCEPT_MASK = (1 << 6) - 1 316 335 }; 317 336 … … 320 339 enum rtl8139_cscr { 321 340 CS_Testfun = (1 << 15), 322 CS_LD = (1 << 9), /**< Low TPI link disable signal */ 323 CS_HEART_BEAT = (1 << 8), /**< Heart beat enable; 10Mbit mode only */ 324 CS_JABBER_ENABLE = (1 << 7), /**< Enable jabber function */ 341 /** Low TPI link disable signal */ 342 CS_LD = (1 << 9), 343 /** Heart beat enable; 10Mbit mode only */ 344 CS_HEART_BEAT = (1 << 8), 345 /** Enable jabber function */ 346 CS_JABBER_ENABLE = (1 << 7), 325 347 CS_F_LINK100 = (1 << 6), 326 348 CS_F_CONNECT = (1 << 5), 327 CS_CON_STATUS = (1 << 3), /**< connection status: 328 * 1 = valid, 0 = disconnected 329 */ 330 CS_CON_STATUS_EN = (1 << 2), /**< LED1 pin connection status indication */ 331 CS_PASS_SCR = (1 << 0) /**< Bypass Scramble */ 349 /** connection status: 1 = valid, 0 = disconnected */ 350 CS_CON_STATUS = (1 << 3), 351 /** LED1 pin connection status indication */ 352 CS_CON_STATUS_EN = (1 << 2), 353 /** Bypass Scramble */ 354 CS_PASS_SCR = (1 << 0) 332 355 }; 333 356 … … 360 383 /** Auto-negotiation advertisement register */ 361 384 enum rtl8139_anar { 362 ANAR_NEXT_PAGE = (1 << 15), /**< Next page bit, 0 - primary capability 363 * 1 - protocol specific 364 */ 365 ANAR_ACK = (1 << 14), /**< Capability reception acknowledge */ 366 ANAR_REMOTE_FAULT = (1 << 13), /**< Remote fault detection capability */ 367 ANAR_PAUSE = (1 << 10), /**< Symetric pause frame capability */ 368 ANAR_100T4 = (1 << 9), /**< T4, not supported by the device */ 369 ANAR_100TX_FD = (1 << 8), /**< 100BASE_TX full duplex */ 370 ANAR_100TX_HD = (1 << 7), /**< 100BASE_TX half duplex */ 371 ANAR_10_FD = (1 << 6), /**< 10BASE_T full duplex */ 372 ANAR_10_HD = (1 << 5), /**< 10BASE_T half duplex */ 373 ANAR_SELECTOR = 0x1 /**< Selector, 374 * CSMA/CD (0x1) supported only 375 */ 385 /** Next page bit, 0 - primary capability, 1 - protocol specific */ 386 ANAR_NEXT_PAGE = (1 << 15), 387 /** Capability reception acknowledge */ 388 ANAR_ACK = (1 << 14), 389 /** Remote fault detection capability */ 390 ANAR_REMOTE_FAULT = (1 << 13), 391 /** Symetric pause frame capability */ 392 ANAR_PAUSE = (1 << 10), 393 /** T4, not supported by the device */ 394 ANAR_100T4 = (1 << 9), 395 /** 100BASE_TX full duplex */ 396 ANAR_100TX_FD = (1 << 8), 397 /** 100BASE_TX half duplex */ 398 ANAR_100TX_HD = (1 << 7), 399 /** 10BASE_T full duplex */ 400 ANAR_10_FD = (1 << 6), 401 /** 10BASE_T half duplex */ 402 ANAR_10_HD = (1 << 5), 403 /** Selector, CSMA/CD (0x1) supported only */ 404 ANAR_SELECTOR = 0x1 376 405 }; 377 406 … … 409 438 410 439 enum rtl8139_config4 { 411 CONFIG4_RxFIFOAutoClr = (1 << 7), /**< Automatic RxFIFO owerflow clear */ 412 CONFIG4_AnaOff = (1 << 6), /**< Analog poweroff */ 413 CONFIG4_LongWF = (1 << 5), /**< Long wakeup frame 414 * (2xCRC8 + 3xCRC16) 415 */ 416 CONFIG4_LWPME = (1 << 4), /**< LWAKE and PMEB assertion */ 417 CONFIG4_LWPTN = (1 << 2), /**< LWake pattern */ 418 CONFIG4_PBWakeup = (1 << 0) /**< Preboot wakeup */ 440 /** Automatic RxFIFO owerflow clear */ 441 CONFIG4_RxFIFOAutoClr = (1 << 7), 442 /** Analog poweroff */ 443 CONFIG4_AnaOff = (1 << 6), 444 /** Long wakeup frame (2xCRC8 + 3xCRC16) */ 445 CONFIG4_LongWF = (1 << 5), 446 /** LWAKE and PMEB assertion */ 447 CONFIG4_LWPME = (1 << 4), 448 /** LWake pattern */ 449 CONFIG4_LWPTN = (1 << 2), 450 /** Preboot wakeup */ 451 CONFIG4_PBWakeup = (1 << 0) 419 452 }; 420 453 … … 438 471 439 472 enum rtl8139_tcr_bits { 440 HWVERID_A_SHIFT = 26, /**< HW version id, part A shift */ 441 HWVERID_A_SIZE = 5, /**< HW version id, part A bit size */ 442 HWVERID_A_MASK = (1 << 5) - 1, /**< HW version id, part A mask */ 443 444 IFG_SHIFT = 24, /**< The interframe gap time setting shift */ 445 IFG_SIZE = 2, /**< The interframe gap time setting bit size */ 446 447 HWVERID_B_SHIFT = 22, /**< HW version id, part B shift */ 448 HWVERID_B_SIZE = 2, /**< HW version id, part B bit size */ 449 HWVERID_B_MASK = (1 << 2) - 1, /**< HW version id, part B mask */ 450 451 LOOPBACK_SHIFT = 17, /**< Loopback mode shift */ 452 LOOPBACK_SIZE = 2, /**< Loopback mode size 453 * 00 = normal, 11 = loopback 454 */ 455 456 APPEND_CRC = 1 << 16, /**< Append CRC at the end of a frame */ 457 458 MXTxDMA_SHIFT = 8, /**< Max. DMA Burst per TxDMA shift, burst = 16^value */ 459 MXTxDMA_SIZE = 3, /**< Max. DMA Burst per TxDMA bit size */ 460 461 TX_RETRY_COUNT_SHIFT = 4, /**< Retries before aborting shift */ 462 TX_RETRY_COUNT_SIZE = 4, /**< Retries before aborting size */ 463 464 CLEAR_ABORT = 1 << 0 /**< Retransmit aborted frame at the last 465 * transmitted descriptor 466 */ 473 /** HW version id, part A shift */ 474 HWVERID_A_SHIFT = 26, 475 /** HW version id, part A bit size */ 476 HWVERID_A_SIZE = 5, 477 /** HW version id, part A mask */ 478 HWVERID_A_MASK = (1 << 5) - 1, 479 480 /** The interframe gap time setting shift */ 481 IFG_SHIFT = 24, 482 /** The interframe gap time setting bit size */ 483 IFG_SIZE = 2, 484 485 /** HW version id, part B shift */ 486 HWVERID_B_SHIFT = 22, 487 /** HW version id, part B bit size */ 488 HWVERID_B_SIZE = 2, 489 /** HW version id, part B mask */ 490 HWVERID_B_MASK = (1 << 2) - 1, 491 492 /** Loopback mode shift */ 493 LOOPBACK_SHIFT = 17, 494 /** Loopback mode size. 00 = normal, 11 = loopback */ 495 LOOPBACK_SIZE = 2, 496 497 /** Append CRC at the end of a frame */ 498 APPEND_CRC = 1 << 16, 499 500 /** Max. DMA Burst per TxDMA shift, burst = 16^value */ 501 MXTxDMA_SHIFT = 8, 502 /** Max. DMA Burst per TxDMA bit size */ 503 MXTxDMA_SIZE = 3, 504 505 /** Retries before aborting shift */ 506 TX_RETRY_COUNT_SHIFT = 4, 507 /** Retries before aborting size */ 508 TX_RETRY_COUNT_SIZE = 4, 509 510 /** Retransmit aborted frame at the last transmitted descriptor */ 511 CLEAR_ABORT = 1 << 0 467 512 }; 468 513
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