Changeset 904b1bc in mainline for kernel/arch/arm32/include/arch/cp15.h

Timestamp:

2018-05-22T10:36:58Z (6 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a4eb3ba2

Parents:

4f8772d4

git-author:

Jiri Svoboda <jiri@…> (2018-05-21 17:36:30)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-22 10:36:58)

Message:

Fix remaining ccheck issues.

File:

• kernel/arch/arm32/include/arch/cp15.h (modified) (5 diffs)

kernel/arch/arm32/include/arch/cp15.h

@@ -40 +40 @@
 
 /** See ARM Architecture reference manual ch. B3.17.1 page B3-1456
- * for the list */
+ * for the list
+ */
 
 #define CONTROL_REG_GEN_READ(name, crn, opc1, crm, opc2) \
@@ -183 +184 @@
         CCSIDR_LINESIZE_MASK = 0x7,
         CCSIDR_LINESIZE_SHIFT = 0,
+};
+
 #define CCSIDR_SETS(val) \
         (((val >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK) + 1)
@@ -190 +193 @@
 #define CCSIDR_LINESIZE_LOG(val) \
         (((val >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK) + 2 + 2)
-};
+
 CONTROL_REG_GEN_READ(CCSIDR, c0, 1, c0, 0);
 
@@ -206 +209 @@
         CLIDR_UNI_CACHE = 0x4,
         CLIDR_CACHE_MASK = 0x7,
+};
+
 /** levels counted from 0 */
 #define CLIDR_CACHE(level, val)   ((val >> (level * 3)) & CLIDR_CACHE_MASK)
-};
+
 CONTROL_REG_GEN_READ(CLIDR, c0, 1, c0, 1);
 CONTROL_REG_GEN_READ(AIDR, c0, 1, c0, 7); /* Implementation defined or MIDR */
@@ -225 +230 @@
 
 /* System control registers */
-/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
- * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+/*
+ * Control register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687
+ */
 enum {
         SCTLR_MMU_EN_FLAG            = 1 << 0,