Changeset 8b655705 in mainline for boot/arch/mips32/src/asm.S

Timestamp:

2011-04-15T19:38:07Z (13 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9dd730d1

Parents:

6b9e85b (diff), b2fb47f (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• boot/arch/mips32/src/asm.S (modified) (3 diffs)

boot/arch/mips32/src/asm.S

@@ -41 +41 @@
 
 start:
-        /* Setup CPU map (on msim this code
-           is executed in parallel on all CPUs,
-           but it not an issue) */
+        /*
+         * Setup the CP0 configuration
+         *  - Disable 64-bit kernel addressing mode
+         *  - DIsable 64-bit supervisor adressing mode
+         *  - Disable 64-bit user addressing mode
+         */
+        mfc0 $a0, $status
+        la $a1, 0xffffff1f
+        and $a0, $a1, $a0
+        mtc0 $a0, $status
+        
+        /*
+         * Setup CPU map (on msim this code
+         * is executed in parallel on all CPUs,
+         * but it not an issue).
+         */
         la $a0, PA2KA(CPUMAP_OFFSET)
         
@@ -94 +107 @@
         lw $k1, ($k0)
         
-        /* If we are not running on BSP
-           then end in an infinite loop  */
+        /*
+         * If we are not running on BSP
+         * then end in an infinite loop.
+         */
         beq $k1, $zero, bsp
         nop
@@ -127 +142 @@
 
 jump_to_kernel:
-        #
-        # TODO:
-        # Make sure that the I-cache, D-cache and memory are mutually coherent
-        # before passing control to the copied code.
-        #
+        /*
+         * TODO:
+         *
+         * Make sure that the I-cache, D-cache and memory are mutually
+         * coherent before passing control to the copied code.
+         */
         j $a0
         nop