Changeset 8abcf4e in mainline


Ignore:
Timestamp:
2013-08-04T12:41:47Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f9f758e
Parents:
186b919
Message:

armv7: Fix dcache flushing routines.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/cpu/cpu.c

    r186b919 r8abcf4e  
    157157#endif
    158158#ifdef PROCESSOR_ARCH_armv7_a
    159          /* ICache coherency is elaborate on in barrier.h.
     159         /* ICache coherency is elaborated on in barrier.h.
    160160          * VIPT and PIPT caches need maintenance only on code modify,
    161161          * so it should be safe for general use.
     
    204204#ifdef PROCESSOR_ARCH_armv7_a
    205205        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    206         const unsigned ls_log = 2 +
    207             ((CCSIDR_read() >> CCSIDR_LINESIZE_SHIFT) & CCSIDR_LINESIZE_MASK);
    208         return ls_log + 2; //return log2(bytes)
     206        const uint32_t ccsidr = CCSIDR_read();
     207        return CCSIDR_LINESIZE_LOG(ccsidr);
    209208#endif
    210209        return 0;
     
    217216#ifdef PROCESSOR_ARCH_armv7_a
    218217        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    219         const unsigned ways = 1 +
    220             ((CCSIDR_read() >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK);
    221         return ways;
     218        const uint32_t ccsidr = CCSIDR_read();
     219        return CCSIDR_WAYS(ccsidr);
    222220#endif
    223221        return 0;
     
    229227#ifdef PROCESSOR_ARCH_armv7_a
    230228        CSSELR_write((level & CCSELR_LEVEL_MASK) << CCSELR_LEVEL_SHIFT);
    231         const unsigned sets = 1 +
    232             ((CCSIDR_read() >> CCSIDR_NUMSETS_SHIFT) & CCSIDR_NUMSETS_MASK);
    233         return sets;
     229        const uint32_t ccsidr = CCSIDR_read();
     230        return CCSIDR_SETS(ccsidr);
    234231#endif
    235232        return 0;
     
    241238#ifdef PROCESSOR_ARCH_armv7_a
    242239        const uint32_t val = CLIDR_read();
    243         for (unsigned i = 1; i <= 7; ++i) {
     240        for (unsigned i = 0; i < 7; ++i) {
    244241                const unsigned ctype = CLIDR_CACHE(i, val);
    245242                switch (ctype) {
     
    280277                const unsigned ways = dcache_ways(i);
    281278                const unsigned sets = dcache_sets(i);
    282                 const unsigned way_shift =  31 - log2(ways);
     279                const unsigned way_shift = 32 - log2(ways);
    283280                const unsigned set_shift = dcache_linesize_log(i);
    284281                dcache_clean_manual(i, false, ways, sets, way_shift, set_shift);
     
    293290                const unsigned ways = dcache_ways(i);
    294291                const unsigned sets = dcache_sets(i);
    295                 const unsigned way_shift =  31 - log2(ways);
     292                const unsigned way_shift = 32 - log2(ways);
    296293                const unsigned set_shift = dcache_linesize_log(i);
    297294                dcache_clean_manual(i, true, ways, sets, way_shift, set_shift);
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