Changeset 8ab339e in mainline for kernel/arch/arm32/src/mm/page_fault.c

Timestamp:

2013-02-26T10:58:29Z (11 years ago)

Author:

Vojtech Horky <vojtechhorky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b04ca9c

Parents:

1935591 (diff), 088b334 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes

File:

• kernel/arch/arm32/src/mm/page_fault.c (modified) (4 diffs)

kernel/arch/arm32/src/mm/page_fault.c

@@ -34 +34 @@
  */
 #include <panic.h>
+#include <arch/cp15.h>
 #include <arch/exception.h>
 #include <arch/mm/page_fault.h>
@@ -127 +128 @@
 }
 
-
-/** Returns value stored in comnbined/data fault status register.
- *
- *  @return Value stored in CP15 fault status register (FSR).
- *
- *  "VMSAv6 added a fifth fault status bit (bit[10]) to both the IFSR and DFSR.
- *  It is IMPLEMENTATION DEFINED how this bit is encoded in earlier versions of
- *  the architecture. A write flag (bit[11] of the DFSR) has also been
- *  introduced."
- *  ARM Architecture Reference Manual version i ch. B4.6 (PDF p. 719)
- *
- *  See ch. B4.9.6 for location of data/instruction FSR.
- *
- */
-static inline fault_status_t read_data_fault_status_register(void)
-{
-        fault_status_t fsu;
-        
-        /* Combined/Data fault status is stored in CP15 register 5, c0. */
-        asm volatile (
-                "mrc p15, 0, %[dummy], c5, c0, 0"
-                : [dummy] "=r" (fsu.raw)
-        );
-        
-        return fsu;
-}
-
-/** Returns DFAR (fault address register) content.
- *
- * This register is equivalent to FAR on pre armv6 machines.
- *
- * @return DFAR (fault address register) content (address that caused a page
- *         fault)
- */
-static inline uintptr_t read_data_fault_address_register(void)
-{
-        uintptr_t ret;
-        
-        /* fault adress is stored in CP15 register 6 */
-        asm volatile (
-                "mrc p15, 0, %[ret], c6, c0, 0"
-                : [ret] "=r" (ret)
-        );
-        
-        return ret;
-}
-
-#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
 /** Decides whether read or write into memory is requested.
  *
@@ -244 +198 @@
 void data_abort(unsigned int exc_no, istate_t *istate)
 {
-        const uintptr_t badvaddr = read_data_fault_address_register();
-        const fault_status_t fsr = read_data_fault_status_register();
+        const uintptr_t badvaddr = DFAR_read();
+        const fault_status_t fsr = { .raw = DFSR_read() };
         const dfsr_source_t source = fsr.raw & DFSR_SOURCE_MASK;
 
@@ -281 +235 @@
         }
 
-#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
+#if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
         const pf_access_t access =
             fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
-#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
+#elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
         const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
 #else