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Changeset 89cefe78 in mainline for uspace/drv/bus/usb/xhci/endpoint.h


Ignore:
Timestamp:
2017-10-22T21:47:55Z (5 years ago)
Author:
Petr Manek <petr.manek@…>
Branches:
lfn, master, serial
Children:
82fe063
Parents:
ee794529
Message:

Refactored transfer DS allocation in preparation for streams. Also, converted EP context setup to table.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/usb/xhci/endpoint.h

    ree794529 r89cefe78  
    6565        endpoint_t base;        /**< Inheritance. Keep this first. */
    6666
    67         /** Main TRB ring */
     67        /** Main TRB ring (or NULL if endpoint uses streams) */
    6868        xhci_trb_ring_t ring;
    6969
     
    7272         * endpoint_t */
    7373        xhci_transfer_t active_transfer;
     74
     75        /** Primary stream context array (or NULL if endpoint doesn't use streams) */
     76        xhci_stream_ctx_t *primary_stream_ctx_array;
     77
     78        /** Maximum number of streams, also a valid range of PSCA above */
     79        uint16_t max_streams;
     80
     81        /* FIXME: Figure out type for these two fields. */
     82        uint8_t max_burst;
     83        uint8_t mult;
    7484} xhci_endpoint_t;
    7585
     
    101111int xhci_endpoint_init(xhci_endpoint_t *, xhci_bus_t *);
    102112void xhci_endpoint_fini(xhci_endpoint_t *);
     113int xhci_endpoint_alloc_transfer_ds(xhci_endpoint_t *);
     114int xhci_endpoint_free_transfer_ds(xhci_endpoint_t *);
    103115
    104116uint8_t xhci_endpoint_dci(xhci_endpoint_t *);
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