Changeset 86ffa27f in mainline for uspace/drv/bus/usb/ohci/ohci_regs.h


Ignore:
Timestamp:
2011-08-07T11:21:44Z (13 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
cc574511
Parents:
15f3c3f (diff), e8067c0 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/usb/ohci/ohci_regs.h

    r15f3c3f r86ffa27f  
    3434#ifndef DRV_OHCI_OHCI_REGS_H
    3535#define DRV_OHCI_OHCI_REGS_H
    36 #include <stdint.h>
     36#include <sys/types.h>
     37
     38#define LEGACY_REGS_OFFSET 0x100
    3739
    3840/** OHCI memory mapped registers structure */
    3941typedef struct ohci_regs {
    40         const volatile uint32_t revision;
    41         volatile uint32_t control;
    42 #define C_CSBR_MASK (0x3) /* Control-bulk service ratio */
    43 #define C_CSBR_1_1  (0x0)
    44 #define C_CSBR_1_2  (0x1)
    45 #define C_CSBR_1_3  (0x2)
    46 #define C_CSBR_1_4  (0x3)
    47 #define C_CSBR_SHIFT (0)
     42        const ioport32_t revision;
     43#define R_REVISION_MASK (0x3f)
     44#define R_REVISION_SHIFT (0)
     45#define R_LEGACY_FLAG   (0x80)
     46
     47        ioport32_t control;
     48#define C_CBSR_MASK (0x3) /* Control-bulk service ratio */
     49#define C_CBSR_1_1  (0x0)
     50#define C_CBSR_1_2  (0x1)
     51#define C_CBSR_1_3  (0x2)
     52#define C_CBSR_1_4  (0x3)
     53#define C_CBSR_SHIFT (0)
    4854
    4955#define C_PLE (1 << 2)   /* Periodic list enable */
     
    5965#define C_HCFS_SHIFT       (6)
    6066
     67#define C_HCFS_GET(reg) \
     68        ((reg >> C_HCFS_SHIFT) & C_HCFS_MASK)
     69#define C_HCFS_SET(reg, hcfs_state) \
     70do { \
     71        reg = (reg & ~(C_HCFS_MASK << C_HCFS_SHIFT)) \
     72            | ((hcfs_state & C_HCFS_MASK) << C_HCFS_SHIFT); \
     73} while (0)
     74
     75
    6176#define C_IR  (1 << 8)   /* Interrupt routing, make sure it's 0 */
    6277#define C_RWC (1 << 9)   /* Remote wakeup connected, host specific */
    6378#define C_RWE (1 << 10)  /* Remote wakeup enable */
    6479
    65         volatile uint32_t command_status;
     80        ioport32_t command_status;
    6681#define CS_HCR (1 << 0)   /* Host controller reset */
    6782#define CS_CLF (1 << 1)   /* Control list filled */
     
    7590         * writing causes enable/disable,
    7691         * status is write-clean (writing 1 clears the bit*/
    77         volatile uint32_t interrupt_status;
    78         volatile uint32_t interrupt_enable;
    79         volatile uint32_t interrupt_disable;
     92        ioport32_t interrupt_status;
     93        ioport32_t interrupt_enable;
     94        ioport32_t interrupt_disable;
    8095#define I_SO   (1 << 0)   /* Scheduling overrun */
    8196#define I_WDH  (1 << 1)   /* Done head write-back */
     
    89104
    90105        /** HCCA pointer (see hw_struct hcca.h) */
    91         volatile uint32_t hcca;
     106        ioport32_t hcca;
    92107#define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */
    93108
    94109        /** Currently executed periodic endpoint */
    95         const volatile uint32_t periodic_current;
     110        const ioport32_t periodic_current;
    96111
    97112        /** The first control endpoint */
    98         volatile uint32_t control_head;
     113        ioport32_t control_head;
    99114
    100115        /** Currently executed control endpoint */
    101         volatile uint32_t control_current;
     116        ioport32_t control_current;
    102117
    103118        /** The first bulk endpoint */
    104         volatile uint32_t bulk_head;
     119        ioport32_t bulk_head;
    105120
    106121        /** Currently executed bulk endpoint */
    107         volatile uint32_t bulk_current;
     122        ioport32_t bulk_current;
    108123
    109124        /** Done TD list, this value is periodically written to HCCA */
    110         const volatile uint32_t done_head;
     125        const ioport32_t done_head;
    111126
    112127        /** Frame time and max packet size for all transfers */
    113         volatile uint32_t fm_interval;
     128        ioport32_t fm_interval;
    114129#define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/
    115130#define FMI_FI_SHIFT (0)
     
    119134
    120135        /** Bit times remaining in current frame */
    121         const volatile uint32_t fm_remaining;
     136        const ioport32_t fm_remaining;
    122137#define FMR_FR_MASK FMI_FI_MASK
    123138#define FMR_FR_SHIFT FMI_FI_SHIFT
     
    125140
    126141        /** Frame number */
    127         const volatile uint32_t fm_number;
     142        const ioport32_t fm_number;
    128143#define FMN_NUMBER_MASK (0xffff)
    129144
    130145        /** Remaining bit time in frame to start periodic transfers */
    131         volatile uint32_t periodic_start;
     146        ioport32_t periodic_start;
    132147#define PS_PS_MASK (0x3fff) /* bit time when periodic get priority (0x3e67) */
    133148
    134149        /** Threshold for starting LS transaction */
    135         volatile uint32_t ls_threshold;
     150        ioport32_t ls_threshold;
    136151#define LST_LST_MASK (0x7fff)
    137152
    138153        /** The first root hub control register */
    139         volatile uint32_t rh_desc_a;
     154        ioport32_t rh_desc_a;
    140155#define RHDA_NDS_MASK (0xff) /* Number of downstream ports, max 15 */
    141156#define RHDA_NDS_SHIFT (0)
     
    144159#define RHDA_DT_FLAG   (1 << 10) /* 1-Compound device, must be 0 */
    145160#define RHDA_OCPM_FLAG (1 << 11) /* Over-current mode: 0-global, 1-per port */
    146 #define RHDA_NOCP      (1 << 12) /* OC control: 0-use OCPM, 1-OC off */
     161#define RHDA_NOCP_FLAG (1 << 12) /* OC control: 0-use OCPM, 1-OC off */
    147162#define RHDA_POTPGT_MASK (0xff)  /* Power on to power good time */
    148163#define RHDA_POTPGT_SHIFT (24)
    149164
    150165        /** The other root hub control register */
    151         volatile uint32_t rh_desc_b;
     166        ioport32_t rh_desc_b;
    152167#define RHDB_DR_MASK (0xffff) /* Device removable mask */
    153168#define RHDB_DR_SHIFT (0)
     
    161176
    162177        /** Root hub status register */
    163         volatile uint32_t rh_status;
     178        ioport32_t rh_status;
    164179#define RHS_LPS_FLAG  (1 <<  0)/* read: 0,
    165180                                * write: 0-no effect,
     
    167182                                *        specified in PPCM(RHDB), or all ports,
    168183                                *        if power is set globally */
    169 #define RHS_CLEAR_PORT_POWER RHS_LPS_FLAG /* synonym for the above */
     184#define RHS_CLEAR_GLOBAL_POWER RHS_LPS_FLAG /* synonym for the above */
    170185#define RHS_OCI_FLAG  (1 <<  1)/* Over-current indicator, if per-port: 0 */
    171186#define RHS_DRWE_FLAG (1 << 15)/* read: 0-connect status change does not wake HC
     
    178193                                *        specified in PPCM(RHDB), or all ports,
    179194                                *        if power is set globally */
    180 #define RHS_SET_PORT_POWER RHS_LPSC_FLAG /* synonym for the above */
     195#define RHS_SET_GLOBAL_POWER RHS_LPSC_FLAG /* synonym for the above */
    181196#define RHS_OCIC_FLAG (1 << 17)/* Over-current indicator change   */
    182197#define RHS_CLEAR_DRWE (1 << 31)
    183198
    184199        /** Root hub per port status */
    185         volatile uint32_t rh_port_status[];
     200        ioport32_t rh_port_status[];
    186201#define RHPS_CCS_FLAG (1 << 0) /* r: current connect status,
    187202                                * w: 1-clear port enable, 0-nothing */
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