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Changeset 84439d7 in mainline for kernel/arch/ia32/include/smp/apic.h


Ignore:
Timestamp:
2010-12-05T09:34:46Z (11 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master
Children:
75732da
Parents:
56b962d (diff), 35537a7 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge with development/

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/include/smp/apic.h

    r56b962d r84439d7  
    4949
    5050/** Delivery modes. */
    51 #define DELMOD_FIXED    0x0
    52 #define DELMOD_LOWPRI   0x1
    53 #define DELMOD_SMI      0x2
     51#define DELMOD_FIXED    0x0U
     52#define DELMOD_LOWPRI   0x1U
     53#define DELMOD_SMI      0x2U
    5454/* 0x3 reserved */
    55 #define DELMOD_NMI      0x4
    56 #define DELMOD_INIT     0x5
    57 #define DELMOD_STARTUP  0x6
    58 #define DELMOD_EXTINT   0x7
     55#define DELMOD_NMI      0x4U
     56#define DELMOD_INIT     0x5U
     57#define DELMOD_STARTUP  0x6U
     58#define DELMOD_EXTINT   0x7U
    5959
    6060/** Destination modes. */
    61 #define DESTMOD_PHYS   0x0
    62 #define DESTMOD_LOGIC  0x1
     61#define DESTMOD_PHYS   0x0U
     62#define DESTMOD_LOGIC  0x1U
    6363
    6464/** Trigger Modes. */
    65 #define TRIGMOD_EDGE   0x0
    66 #define TRIGMOD_LEVEL  0x1
     65#define TRIGMOD_EDGE   0x0U
     66#define TRIGMOD_LEVEL  0x1U
    6767
    6868/** Levels. */
    69 #define LEVEL_DEASSERT  0x0
    70 #define LEVEL_ASSERT    0x1
     69#define LEVEL_DEASSERT  0x0U
     70#define LEVEL_ASSERT    0x1U
    7171
    7272/** Destination Shorthands. */
    73 #define SHORTHAND_NONE      0x0
    74 #define SHORTHAND_SELF      0x1
    75 #define SHORTHAND_ALL_INCL  0x2
    76 #define SHORTHAND_ALL_EXCL  0x3
     73#define SHORTHAND_NONE      0x0U
     74#define SHORTHAND_SELF      0x1U
     75#define SHORTHAND_ALL_INCL  0x2U
     76#define SHORTHAND_ALL_EXCL  0x3U
    7777
    7878/** Interrupt Input Pin Polarities. */
    79 #define POLARITY_HIGH  0x0
    80 #define POLARITY_LOW   0x1
     79#define POLARITY_HIGH  0x0U
     80#define POLARITY_LOW   0x1U
    8181
    8282/** Divide Values. (Bit 2 is always 0) */
    83 #define DIVIDE_2    0x0
    84 #define DIVIDE_4    0x1
    85 #define DIVIDE_8    0x2
    86 #define DIVIDE_16   0x3
    87 #define DIVIDE_32   0x8
    88 #define DIVIDE_64   0x9
    89 #define DIVIDE_128  0xa
    90 #define DIVIDE_1    0xb
     83#define DIVIDE_2    0x0U
     84#define DIVIDE_4    0x1U
     85#define DIVIDE_8    0x2U
     86#define DIVIDE_16   0x3U
     87#define DIVIDE_32   0x8U
     88#define DIVIDE_64   0x9U
     89#define DIVIDE_128  0xaU
     90#define DIVIDE_1    0xbU
    9191
    9292/** Timer Modes. */
    93 #define TIMER_ONESHOT   0x0
    94 #define TIMER_PERIODIC  0x1
     93#define TIMER_ONESHOT   0x0U
     94#define TIMER_PERIODIC  0x1U
    9595
    9696/** Delivery status. */
    97 #define DELIVS_IDLE     0x0
    98 #define DELIVS_PENDING  0x1
     97#define DELIVS_IDLE     0x0U
     98#define DELIVS_PENDING  0x1U
    9999
    100100/** Destination masks. */
    101 #define DEST_ALL  0xff
     101#define DEST_ALL  0xffU
    102102
    103103/** Dest format models. */
    104 #define MODEL_FLAT     0xf
    105 #define MODEL_CLUSTER  0x0
     104#define MODEL_FLAT     0xfU
     105#define MODEL_CLUSTER  0x0U
    106106
    107107/** Interrupt Command Register. */
    108 #define ICRlo  (0x300 / sizeof(uint32_t))
    109 #define ICRhi  (0x310 / sizeof(uint32_t))
     108#define ICRlo  (0x300U / sizeof(uint32_t))
     109#define ICRhi  (0x310U / sizeof(uint32_t))
    110110
    111111typedef struct {
     
    135135
    136136/* End Of Interrupt. */
    137 #define EOI  (0x0b0 / sizeof(uint32_t))
     137#define EOI  (0x0b0U / sizeof(uint32_t))
    138138
    139139/** Error Status Register. */
    140 #define ESR  (0x280 / sizeof(uint32_t))
     140#define ESR  (0x280U / sizeof(uint32_t))
    141141
    142142typedef union {
     
    157157
    158158/* Task Priority Register */
    159 #define TPR  (0x080 / sizeof(uint32_t))
     159#define TPR  (0x080U / sizeof(uint32_t))
    160160
    161161typedef union {
     
    168168
    169169/** Spurious-Interrupt Vector Register. */
    170 #define SVR  (0x0f0 / sizeof(uint32_t))
     170#define SVR  (0x0f0U / sizeof(uint32_t))
    171171
    172172typedef union {
     
    181181
    182182/** Time Divide Configuration Register. */
    183 #define TDCR  (0x3e0 / sizeof(uint32_t))
     183#define TDCR  (0x3e0U / sizeof(uint32_t))
    184184
    185185typedef union {
     
    192192
    193193/* Initial Count Register for Timer */
    194 #define ICRT  (0x380 / sizeof(uint32_t))
     194#define ICRT  (0x380U / sizeof(uint32_t))
    195195
    196196/* Current Count Register for Timer */
    197 #define CCRT  (0x390 / sizeof(uint32_t))
     197#define CCRT  (0x390U / sizeof(uint32_t))
    198198
    199199/** LVT Timer register. */
    200 #define LVT_Tm  (0x320 / sizeof(uint32_t))
     200#define LVT_Tm  (0x320U / sizeof(uint32_t))
    201201
    202202typedef union {
     
    214214
    215215/** LVT LINT registers. */
    216 #define LVT_LINT0  (0x350 / sizeof(uint32_t))
    217 #define LVT_LINT1  (0x360 / sizeof(uint32_t))
     216#define LVT_LINT0  (0x350U / sizeof(uint32_t))
     217#define LVT_LINT1  (0x360U / sizeof(uint32_t))
    218218
    219219typedef union {
     
    233233
    234234/** LVT Error register. */
    235 #define LVT_Err  (0x370 / sizeof(uint32_t))
     235#define LVT_Err  (0x370U / sizeof(uint32_t))
    236236
    237237typedef union {
     
    248248
    249249/** Local APIC ID Register. */
    250 #define L_APIC_ID  (0x020 / sizeof(uint32_t))
     250#define L_APIC_ID  (0x020U / sizeof(uint32_t))
    251251
    252252typedef union {
     
    259259
    260260/** Local APIC Version Register */
    261 #define LAVR       (0x030 / sizeof(uint32_t))
    262 #define LAVR_Mask  0xff
    263 
    264 #define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
    265 #define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
    266 #define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
     261#define LAVR       (0x030U / sizeof(uint32_t))
     262#define LAVR_Mask  0xffU
     263
     264#define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0U) == 0x1U)
     265#define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0U) == 0x0U))
     266#define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14U)
    267267
    268268/** Logical Destination Register. */
    269 #define  LDR  (0x0d0 / sizeof(uint32_t))
     269#define  LDR  (0x0d0U / sizeof(uint32_t))
    270270
    271271typedef union {
     
    278278
    279279/** Destination Format Register. */
    280 #define DFR  (0x0e0 / sizeof(uint32_t))
     280#define DFR  (0x0e0U / sizeof(uint32_t))
    281281
    282282typedef union {
     
    289289
    290290/* IO APIC */
    291 #define IOREGSEL  (0x00 / sizeof(uint32_t))
    292 #define IOWIN     (0x10 / sizeof(uint32_t))
    293 
    294 #define IOAPICID   0x00
    295 #define IOAPICVER  0x01
    296 #define IOAPICARB  0x02
    297 #define IOREDTBL   0x10
     291#define IOREGSEL  (0x00U / sizeof(uint32_t))
     292#define IOWIN     (0x10U / sizeof(uint32_t))
     293
     294#define IOAPICID   0x00U
     295#define IOAPICVER  0x01U
     296#define IOAPICARB  0x02U
     297#define IOREDTBL   0x10U
    298298
    299299/** I/O Register Select Register. */
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