Changeset 83742a4 in mainline for boot/arch/arm32/src/asm.S


Ignore:
Timestamp:
2013-01-20T16:02:33Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
b8bb2bc
Parents:
4a79e6f
Message:

arm32: Add cache maintenance to jump_to_kernel, enable caches on bbxm boot.

BBXM boots significantly faster.
Should be generic enough for all ARMs.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/asm.S

    r4a79e6f r83742a4  
    6161        #
    6262
     63        #
     64        # r0 is kernel entry point
     65        # r1 is pointer to the bootinfo structure
     66        # r2 is a kernel text end
     67
     68        # make sure kernel is flushed and available in memory
     69        # Disable I-cache and D-cache before the kernel is started.
     70        # TODO disabling DCache should not be necessary...
     71#define CP15_C1_IC              12
     72#define CP15_C1_DC              2
     73        mrc     p15, 0, r4, c1, c0, 0
     74        bic     r4, r4, #(1 << CP15_C1_DC)
     75        bic     r4, r4, #(1 << CP15_C1_IC)
     76        mcr     p15, 0, r4, c1, c0, 0
     77
     78        # use r4 as a moving pointer
     79        mov r4, r0
     803:
     81        # DCCMVAC (flush by virt address, to the point of coherence)
     82        mcr p15, 0, r4, c7, c10, 1
     83        # TODO: it would be better to use cacheline size
     84        add r4, r4, #4
     85        # are we there yet?
     86        cmp r4, r2
     87        blt 3b
     88        nop
     89        mov r4, #0
     90       
     91        #Wait for the operations to complete
     92#ifdef PROCESSOR_ARCH_armv7_a
     93        dsb
     94#else
     95        #cp15 dsb, r4 is ignored (should be zero)
     96        mcr p15, 0, r4, c7, c10, 4
     97#endif
     98       
     99        # Clean ICache and BPredictors, r4 ignored (SBZ)
     100        mcr p15, 0, r4, c7, c5, 0
     101
     102        #Wait for the operations to complete
     103#ifdef PROCESSOR_ARCH_armv7_a
     104        isb
     105#else
     106        # cp15 isb
     107        mcr p15, 0, r4, c7, c5, 4
     108#endif
     109       
     110
    63111#if defined(MACHINE_gta02)
    64112
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