Changeset 816335c in mainline for uspace/drv/bus/usb/xhci/hc.c
- Timestamp:
- 2017-10-04T10:06:10Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- c68c713c
- Parents:
- 5c5c9407
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/hc.c
r5c5c9407 r816335c 48 48 */ 49 49 #define PSI_TO_BPS(psie, psim) (((uint64_t) psim) << (10 * psie)) 50 #define PORT_SPEED(psie, psim) { \ 50 #define PORT_SPEED(mjr, psie, psim) { \ 51 .name = "USB ", \ 52 .major = mjr, \ 53 .minor = 0, \ 51 54 .rx_bps = PSI_TO_BPS(psie, psim), \ 52 55 .tx_bps = PSI_TO_BPS(psie, psim) \ 53 56 } 54 static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 12);55 static const xhci_port_speed_t ps_default_low = PORT_SPEED( 1, 1500);56 static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 480);57 static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 5);57 static const xhci_port_speed_t ps_default_full = PORT_SPEED(2, 2, 12); 58 static const xhci_port_speed_t ps_default_low = PORT_SPEED(2, 1, 1500); 59 static const xhci_port_speed_t ps_default_high = PORT_SPEED(2, 2, 480); 60 static const xhci_port_speed_t ps_default_super = PORT_SPEED(3, 3, 5); 58 61 59 62 /** … … 62 65 static int hc_parse_ec(xhci_hc_t *hc) 63 66 { 64 unsigned psic, major; 67 unsigned psic, major, minor; 68 xhci_sp_name_t name; 69 70 xhci_port_speed_t *speeds = hc->rh.speeds; 65 71 66 72 for (xhci_extcap_t *ec = hc->xecp; ec; ec = xhci_extcap_next(ec)) { … … 74 80 psic = XHCI_REG_RD(ec, XHCI_EC_SP_PSIC); 75 81 major = XHCI_REG_RD(ec, XHCI_EC_SP_MAJOR); 82 minor = XHCI_REG_RD(ec, XHCI_EC_SP_MINOR); 83 name.packed = host2uint32_t_le(XHCI_REG_RD(ec, XHCI_EC_SP_NAME)); 84 85 if (name.packed != xhci_name_usb.packed) { 86 /** 87 * The detection of such protocol would work, 88 * but the rest of the implementation is made 89 * for the USB protocol only. 90 */ 91 usb_log_error("Unknown protocol %.4s.", name.str); 92 return ENOTSUP; 93 } 76 94 77 95 // "Implied" speed 78 96 if (psic == 0) { 79 /* 80 * According to section 7.2.2.1.2, only USB 2.0 81 * and USB 3.0 can have psic == 0. So we 82 * blindly assume the name == "USB " and minor 83 * == 0. 84 */ 85 86 unsigned ports_from = XHCI_REG_RD(ec, XHCI_EC_SP_CP_OFF); 87 unsigned ports_to = ports_from 88 + XHCI_REG_RD(ec, XHCI_EC_SP_CP_COUNT) - 1; 97 assert(minor == 0); 89 98 90 99 if (major == 2) { 91 hc->speeds[1] = ps_default_full; 92 hc->speeds[2] = ps_default_low; 93 hc->speeds[3] = ps_default_high; 94 hc->rh.usb2_port_start = ports_from; 95 hc->rh.usb2_port_end = ports_to; 100 speeds[1] = ps_default_full; 101 speeds[2] = ps_default_low; 102 speeds[3] = ps_default_high; 96 103 } else if (major == 3) { 97 hc->speeds[4] = ps_default_super; 98 hc->rh.usb3_port_start = ports_from; 99 hc->rh.usb3_port_end = ports_to; 104 speeds[4] = ps_default_super; 100 105 } else { 101 106 return EINVAL; 102 107 } 103 108 104 usb_log_debug2("Implied speed of USB %u set up.", major);109 usb_log_debug2("Implied speed of USB %u.0 set up.", major); 105 110 } else { 106 111 for (unsigned i = 0; i < psic; i++) { … … 111 116 unsigned psim = XHCI_REG_RD(psi, XHCI_PSI_PSIM); 112 117 118 speeds[psiv].major = major; 119 speeds[psiv].minor = minor; 120 str_ncpy(speeds[psiv].name, 4, name.str, 4); 121 113 122 uint64_t bps = PSI_TO_BPS(psie, psim); 114 123 115 124 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_RX) 116 hc->speeds[psiv].rx_bps = bps;125 speeds[psiv].rx_bps = bps; 117 126 if (sim == XHCI_PSI_PLT_SYMM || sim == XHCI_PSI_PLT_TX) { 118 hc->speeds[psiv].tx_bps = bps;119 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, hc->speeds[psiv].rx_bps, hc->speeds[psiv].tx_bps);127 speeds[psiv].tx_bps = bps; 128 usb_log_debug2("Speed %u set up for bps %" PRIu64 " / %" PRIu64 ".", psiv, speeds[psiv].rx_bps, speeds[psiv].tx_bps); 120 129 } 121 130 } … … 202 211 goto err_scratch; 203 212 204 if ((err = xhci_rh_init(&hc->rh, hc ->op_regs)))213 if ((err = xhci_rh_init(&hc->rh, hc))) 205 214 goto err_cmd; 206 215
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