Changeset 802898f in mainline for kernel/arch/arm32/include/arch/mm/page_armv6.h
- Timestamp:
- 2013-09-02T20:14:11Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8c95dff
- Parents:
- 0435fe41 (diff), 61ab4a9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/arm32/include/arch/mm/page_armv6.h
r0435fe41 r802898f 40 40 #error "Do not include arch specific page.h directly use generic page.h instead" 41 41 #endif 42 42 43 43 44 /* Macros for querying the last-level PTE entries. */ … … 125 126 #define PTE_DESCRIPTOR_SMALL_PAGE_NX 3 126 127 127 /** Sets the address of level 0 page table. 128 * 129 * @param pt Pointer to the page table to set. 130 * 131 */ 132 NO_TRACE static inline void set_ptl0_addr(pte_t *pt) 133 { 134 asm volatile ( 135 "mcr p15, 0, %[pt], c2, c0, 0\n" 136 :: [pt] "r" (pt) 137 ); 138 } 128 129 /** 130 * For an ARMv7 implementation that does not include the Large Physical Address Extension, 131 * and in implementations of architecture versions before ARMv7, if the translation tables 132 * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of 133 * unification after writing to the translation tables and before the DSB instruction. This 134 * ensures that the updated translation table are visible to a hardware translation table walk. 135 * 136 * Therefore, an example instruction sequence for writing a translation table entry, 137 * covering changes to the instruction 138 * or data mappings in a uniprocessor system is: 139 * STR rx, [Translation table entry] 140 * ; write new entry to the translation table 141 * Clean cache line [Translation table entry] : This operation is not required with the 142 * ; Multiprocessing Extensions. 143 * DSB 144 * ; ensures visibility of the data cleaned from the D Cache 145 * Invalidate TLB entry by MVA (and ASID if non-global) [page address] 146 * Invalidate BTC 147 * DSB 148 * ; ensure completion of the Invalidate TLB operation 149 * ISB 150 * ; ensure table changes visible to instruction fetch 151 * 152 * ARM Architecture reference chp. B3.10.1 p. B3-1375 153 * @note: see TTRB0/1 for pt memory type 154 */ 155 #define pt_coherence_m(pt, count) \ 156 do { \ 157 for (unsigned i = 0; i < count; ++i) \ 158 DCCMVAU_write((uintptr_t)(pt + i)); \ 159 read_barrier(); \ 160 } while (0) 139 161 140 162 … … 206 228 p->ns = 0; 207 229 } 230 pt_coherence(p); 208 231 } 209 232 … … 232 255 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX; 233 256 } 234 235 /* tex=0 buf=1 and cache=1 => normal memory 236 * tex=0 buf=1 and cache=0 => shareable device mmio 237 */ 238 p->cacheable = (flags & PAGE_CACHEABLE); 239 p->bufferable = 1; 240 p->tex = 0; 257 258 if (flags & PAGE_CACHEABLE) { 259 /* 260 * Write-through, no write-allocate memory, see ch. B3.8.2 261 * (p. B3-1358) of ARM Architecture reference manual. 262 * Make sure the memory type is correct, and in sync with: 263 * init_boot_pt (boot/arch/arm32/src/mm.c) 264 * init_ptl0_section (boot/arch/arm32/src/mm.c) 265 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h) 266 */ 267 p->tex = 5; 268 p->cacheable = 0; 269 p->bufferable = 1; 270 } else { 271 /* 272 * Shareable device memory, see ch. B3.8.2 (p. B3-1358) of 273 * ARM Architecture reference manual. 274 */ 275 p->tex = 0; 276 p->cacheable = 0; 277 p->bufferable = 1; 278 } 241 279 242 280 /* Shareable is ignored for devices (non-cacheable), 243 * turn it o nfor normal memory. */244 p->shareable = 1;281 * turn it off for normal memory. */ 282 p->shareable = 0; 245 283 246 284 p->non_global = !(flags & PAGE_GLOBAL); … … 256 294 p->access_permission_1 = PTE_AP1_RO; 257 295 } 296 pt_coherence(p); 258 297 } 259 298 … … 264 303 p->should_be_zero_0 = 0; 265 304 p->should_be_zero_1 = 0; 266 write_barrier();267 305 p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; 306 pt_coherence(p); 268 307 } 269 308 … … 273 312 274 313 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; 314 pt_coherence(p); 275 315 } 276 316
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