Changeset 802898f in mainline for kernel/arch/arm32/include/arch/mm/page.h
- Timestamp:
- 2013-09-02T20:14:11Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8c95dff
- Parents:
- 0435fe41 (diff), 61ab4a9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/arm32/include/arch/mm/page.h
r0435fe41 r802898f 41 41 #include <arch/exception.h> 42 42 #include <arch/barrier.h> 43 #include <arch/cp15.h> 43 44 #include <trace.h> 44 45 … … 95 96 /* Set PTE address accessors for each level. */ 96 97 #define SET_PTL0_ADDRESS_ARCH(ptl0) \ 97 (set_ptl0_addr((pte_t *) (ptl0)))98 set_ptl0_addr((pte_t *) (ptl0)) 98 99 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ 99 (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)100 set_ptl1_addr((pte_t*) (ptl0), i, a) 100 101 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) 101 102 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) 102 103 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ 103 (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)104 set_ptl3_addr((pte_t*) (ptl3), i, a) 104 105 105 106 /* Get PTE flags accessors for each level. */ … … 129 130 set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) 130 131 132 133 #define pt_coherence(page) pt_coherence_m(page, 1) 134 131 135 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a) 132 136 #include "page_armv6.h" … … 137 141 #endif 138 142 143 /** Sets the address of level 0 page table. 144 * 145 * @param pt Pointer to the page table to set. 146 * 147 * Page tables are always in cacheable memory. 148 * Make sure the memory type is correct, and in sync with: 149 * init_boot_pt (boot/arch/arm32/src/mm.c) 150 * init_ptl0_section (boot/arch/arm32/src/mm.c) 151 * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h) 152 */ 153 NO_TRACE static inline void set_ptl0_addr(pte_t *pt) 154 { 155 uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK; 156 val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; 157 TTBR0_write(val); 158 } 159 160 NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address) 161 { 162 pt[i].l0.coarse_table_addr = address >> 10; 163 pt_coherence(&pt[i].l0); 164 } 165 166 NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address) 167 { 168 pt[i].l1.frame_base_addr = address >> 12; 169 pt_coherence(&pt[i].l1); 170 } 171 139 172 #endif 140 173
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