Changeset 7fa2031 in mainline


Ignore:
Timestamp:
2013-01-20T22:17:55Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f03f107
Parents:
96228d0
Message:

amdm37x_dispc: Implement mode changing.

Location:
uspace/drv/fb/amdm37x_dispc
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/fb/amdm37x_dispc/amdm37x_dispc.c

    r96228d0 r7fa2031  
    3636#include <assert.h>
    3737#include <errno.h>
     38#include <ddf/log.h>
     39#include <ddi.h>
     40#include <abi/mm/as.h>
    3841
    3942#include "amdm37x_dispc.h"
    4043
     44
     45static int change_mode(visualizer_t *vis, vslmode_t mode);
    4146static int handle_damage(visualizer_t *vs,
    4247    sysarg_t x0, sysarg_t y0, sysarg_t width, sysarg_t height,
    43     sysarg_t x_offset, sysarg_t y_offset)
    44 {
    45         return EOK;
    46 }
     48    sysarg_t x_offset, sysarg_t y_offset);
    4749
    4850static const visualizer_ops_t amdm37x_dispc_vis_ops = {
     51        .change_mode = change_mode,
    4952        .handle_damage = handle_damage,
    5053        // TODO DO we need dummy implementations of stuff like claim, yield, ...
    5154};
     55
     56
     57static unsigned visual2bpp(visual_t visual)
     58{
     59        switch(visual) {
     60        case VISUAL_INDIRECT_8:
     61                return 1;
     62        case VISUAL_RGB_5_5_5_LE:
     63        case VISUAL_RGB_5_5_5_BE:
     64        case VISUAL_RGB_5_6_5_LE:
     65        case VISUAL_RGB_5_6_5_BE:
     66                return 2;
     67        case VISUAL_BGR_8_8_8:
     68        case VISUAL_RGB_8_8_8:
     69                return 3;
     70        case VISUAL_BGR_0_8_8_8:
     71        case VISUAL_BGR_8_8_8_0:
     72        case VISUAL_ABGR_8_8_8_8:
     73        case VISUAL_BGRA_8_8_8_8:
     74        case VISUAL_RGB_0_8_8_8:
     75        case VISUAL_RGB_8_8_8_0:
     76        case VISUAL_ARGB_8_8_8_8:
     77        case VISUAL_RGBA_8_8_8_8:
     78                return 4;
     79        case VISUAL_UNKNOWN:
     80                return 0;
     81        }
     82        return 0;
     83}
    5284
    5385static void mode_init(vslmode_list_element_t *mode,
    … …  
    74106        assert(vis);
    75107
    76         unsigned width = CONFIG_BFB_WIDTH;
    77         unsigned height = CONFIG_BFB_HEIGHT;
    78         unsigned bpp = CONFIG_BFB_BPP;
    79 
    80         mode_init(&instance->modes[0], width, height, bpp); //TODO convert bpp to visual
     108        instance->fb_data = NULL;
     109        instance->size = 0;
     110
     111        visual_t visual = VISUAL_UNKNOWN;
     112
     113        switch (CONFIG_BFB_BPP) {
     114        case 8: visual = VISUAL_INDIRECT_8; break;
     115        case 16: visual = VISUAL_RGB_5_6_5_LE; break;
     116        case 24: visual = VISUAL_BGR_8_8_8; break;
     117        case 32: visual = VISUAL_RGB_8_8_8_0; break;
     118        default:
     119                return EINVAL;
     120        }
     121
     122        int ret = pio_enable((void*)AMDM37x_DISPC_BASE_ADDRESS,
     123            AMDM37x_DISPC_SIZE, (void**)&instance->regs);
     124        if (ret != EOK) {
     125                return EIO;
     126        }
     127
     128        mode_init(&instance->modes[0],
     129            CONFIG_BFB_WIDTH, CONFIG_BFB_HEIGHT, visual);
    81130
    82131        /* Handle vis stuff */
    … …  
    93142};
    94143
     144static int amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
     145    unsigned x, unsigned y, unsigned bpp, uint32_t pa)
     146{
     147        assert(regs);
     148        /* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
     149         * no idea what parts of that work. */
     150
     151        /* Disable all interrupts */
     152        regs->irqenable = 0;
     153
     154        /* Pixel format specifics*/
     155        uint32_t attrib_pixel_format = 0;
     156        uint32_t control_data_lanes = 0;
     157        switch (bpp)
     158        {
     159        case 32:
     160                attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
     161                control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
     162                break;
     163        case 24:
     164                attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
     165                control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
     166                break;
     167        case 16:
     168                attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
     169                control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
     170                break;
     171        default:
     172                return EINVAL;
     173        }
     174
     175        /* Prepare sizes */
     176        const uint32_t size_reg =
     177            (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK)
     178                << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
     179            (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK)
     180                << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
     181
     182        /* modes taken from u-boot, for 1024x768 */
     183        // TODO replace magic values with actual correct values
     184//      regs->timing_h = 0x1a4024c9;
     185//      regs->timing_v = 0x02c00509;
     186//      regs->pol_freq = 0x00007028;
     187//      regs->divisor  = 0x00010001;
     188
     189        /* setup output */
     190        regs->size_lcd = size_reg;
     191        regs->size_dig = size_reg;
     192
     193        /* Nice blue default color */
     194        regs->default_color[0] = 0x0000ff;
     195        regs->default_color[1] = 0x0000ff;
     196
     197        /* Setup control register */
     198        uint32_t control = 0 |
     199                AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
     200                (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
     201                AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
     202                AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
     203        regs->control = control;
     204
     205        /* No gamma stuff only data */
     206        uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME
     207                    << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
     208        regs->config = config;
     209
     210
     211        /* Set framebuffer base address */
     212        regs->gfx.ba[0] = pa;
     213        regs->gfx.ba[1] = pa;
     214        regs->gfx.position = 0;
     215
     216        /* Setup fb size */
     217        regs->gfx.size = size_reg;
     218
     219        /* Set pixel format */
     220        uint32_t attribs = 0 |
     221            (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
     222        regs->gfx.attributes = attribs;
     223
     224        /* 0x03ff03c0 is the default */
     225        regs->gfx.fifo_threshold = 0x03ff03c0;
     226        /* This value should be stride - width, 1 means next pixel i.e.
     227         * stride == width */
     228        regs->gfx.row_inc = 1;
     229        /* number of bytes to next pixel in BPP multiples */
     230        regs->gfx.pixel_inc = 1;
     231        /* only used if video is played over fb */
     232        regs->gfx.window_skip = 0;
     233        /* Gamma and palette table */
     234        regs->gfx.table_ba = 0;
     235
     236        /* enable frame buffer graphics */
     237        regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
     238        /* Update register values */
     239        regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
     240        regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
     241        /* Enable output */
     242        regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
     243        regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
     244}
     245
     246static int handle_damage(visualizer_t *vs,
     247    sysarg_t x0, sysarg_t y0, sysarg_t width, sysarg_t height,
     248    sysarg_t x_offset, sysarg_t y_offset)
     249{
     250        ddf_log_fatal("Handling damage\n");
     251        return EOK;
     252}
     253
     254static int change_mode(visualizer_t *vis, vslmode_t mode)
     255{
     256        assert(vis);
     257        assert(vis->dev_ctx);
     258
     259        amdm37x_dispc_t *dispc = vis->dev_ctx;
     260        const unsigned bpp = visual2bpp(mode.cell_visual.pixel_visual);
     261        const unsigned x = mode.screen_width;
     262        const unsigned y = mode.screen_height;
     263        ddf_log_note("Setting mode: %ux%ux%u\n", x, y, bpp);
     264        const size_t size = x * y * bpp;
     265        void *buffer, *pa;
     266        int ret = dmamem_map_anonymous(size, AS_AREA_READ | AS_AREA_WRITE,
     267            0, &pa, &buffer);
     268        if (ret != EOK) {
     269                ddf_log_error("Failed to get new FB\n");
     270                return ret;
     271        }
     272        amdm37x_dispc_setup_fb(dispc->regs, x, y, bpp, (uint32_t)pa);
     273
     274        if (dispc->fb_data)
     275                dmamem_unmap_anonymous(dispc->fb_data);
     276        return EOK;
     277}

  • uspace/drv/fb/amdm37x_dispc/amdm37x_dispc_regs.h

    r96228d0 r7fa2031  
    4141#define AMDM37x_DISPC_SIZE 1024
    4242
    43 #include <assert.h>
    4443#include <macros.h>
    4544
    … …  
    280279        ioport32_t vid_preload[2];
    281280
    282 } __attribute__((packed)) amdm37x_dispc_regs_t;
    283 
    284 static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
    285     unsigned x, unsigned y, unsigned bpp, uintptr_t pa)
    286 {
    287         assert(regs);
    288         /* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
    289          * no idea what parts of that work. */
    290 
    291         /* Disable all interrupts */
    292         regs->irqenable = 0;
    293 
    294         /* Pixel format specifics*/
    295         uint32_t attrib_pixel_format = 0;
    296         uint32_t control_data_lanes = 0;
    297         switch (bpp)
    298         {
    299         case 32:
    300                 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
    301                 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
    302                 break;
    303         case 24:
    304                 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
    305                 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
    306                 break;
    307         case 16:
    308                 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
    309                 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
    310                 break;
    311         default:
    312                 assert(false);
    313         }
    314 
    315         /* Prepare sizes */
    316         const uint32_t size_reg =
    317             (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK)
    318                 << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
    319             (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK)
    320                 << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
    321 
    322         /* modes taken from u-boot, for 1024x768 */
    323         // TODO replace magic values with actual correct values
    324 //      regs->timing_h = 0x1a4024c9;
    325 //      regs->timing_v = 0x02c00509;
    326 //      regs->pol_freq = 0x00007028;
    327 //      regs->divisor  = 0x00010001;
    328 
    329         /* setup output */
    330         regs->size_lcd = size_reg;
    331         regs->size_dig = size_reg;
    332 
    333         /* Nice blue default color */
    334         regs->default_color[0] = 0x0000ff;
    335         regs->default_color[1] = 0x0000ff;
    336 
    337         /* Setup control register */
    338         uint32_t control = 0 |
    339                 AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
    340                 (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
    341                 AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
    342                 AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
    343         regs->control = control;
    344 
    345         /* No gamma stuff only data */
    346         uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME
    347                     << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
    348         regs->config = config;
    349 
    350 
    351         /* Set framebuffer base address */
    352         regs->gfx.ba[0] = pa;
    353         regs->gfx.ba[1] = pa;
    354         regs->gfx.position = 0;
    355 
    356         /* Setup fb size */
    357         regs->gfx.size = size_reg;
    358 
    359         /* Set pixel format */
    360         uint32_t attribs = 0 |
    361             (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
    362         regs->gfx.attributes = attribs;
    363 
    364         /* 0x03ff03c0 is the default */
    365         regs->gfx.fifo_threshold = 0x03ff03c0;
    366         /* This value should be stride - width, 1 means next pixel i.e.
    367          * stride == width */
    368         regs->gfx.row_inc = 1;
    369         /* number of bytes to next pixel in BPP multiples */
    370         regs->gfx.pixel_inc = 1;
    371         /* only used if video is played over fb */
    372         regs->gfx.window_skip = 0;
    373         /* Gamma and palette table */
    374         regs->gfx.table_ba = 0;
    375 
    376         /* enable frame buffer graphics */
    377         regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
    378         /* Update register values */
    379         regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
    380         regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
    381         /* Enable output */
    382         regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
    383         regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
    384 }
     281} amdm37x_dispc_regs_t;
     282
    385283
    386284#endif
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