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Changeset 7deca26 in mainline for uspace/drv/block/ahci/ahci_hw.h


Ignore:
Timestamp:
2012-07-22T14:16:22Z (10 years ago)
Author:
Frantisek Princ <frantisek.princ@…>
Branches:
lfn, master
Children:
7df0c2ff
Parents:
0b293a6 (diff), 76c07e4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge with mainline

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/block/ahci/ahci_hw.h

    r0b293a6 r7deca26  
    374374} ahci_ghc_ghc_t;
    375375
    376 /** AHCI GHC register offset. */
    377 #define AHCI_GHC_GHC_REGISTER_OFFSET  1
    378 
    379376/** AHCI Enable mask bit. */
    380377#define AHCI_GHC_GHC_AE  0x80000000
     
    384381
    385382/** AHCI Memory register Interrupt pending register. */
    386 typedef struct {
    387         /** Interrupt pending status, if set, indicates that
    388          * the corresponding port has an interrupt pending.
    389          */
    390         uint32_t u32;
    391 } ahci_ghc_is_t;
     383typedef uint32_t ahci_ghc_is_t;
    392384
    393385/** AHCI GHC register offset. */
    394 #define AHCI_GHC_IS_REGISTER_OFFSET  2 
     386#define AHCI_GHC_IS_REGISTER_OFFSET  2
     387
     388/** AHCI ports registers offset. */
     389#define AHCI_PORTS_REGISTERS_OFFSET  64
     390
     391/** AHCI port registers size. */
     392#define AHCI_PORT_REGISTERS_SIZE  32
     393
     394/** AHCI port IS register offset. */
     395#define AHCI_PORT_IS_REGISTER_OFFSET  4
    395396
    396397/** AHCI Memory register Ports implemented. */
     
    531532        uint32_t ghc;
    532533        /** Interrupt Status */
    533         uint32_t is;
     534        ahci_ghc_is_t is;
    534535        /** Ports Implemented */
    535536        uint32_t pi;
     
    603604
    604605/** AHCI Memory register Port x Interrupt Status. */
    605 typedef union {
    606         struct {
    607                 /** Device to Host Register FIS Interrupt. */
    608                 unsigned int dhrs : 1;
    609                 /** PIO Setup FIS Interrupt. */
    610                 unsigned int pss : 1;
    611                 /** DMA Setup FIS Interrupt. */
    612                 unsigned int dss : 1;
    613                 /** Set Device Bits Interrupt. */
    614                 unsigned int sdbs : 1;
    615                 /** Unknown FIS Interrupt. */
    616                 unsigned int ufs : 1;
    617                 /** Descriptor Processed. */
    618                 unsigned int dps : 1;
    619                 /** Port Connect Change Status. */
    620                 unsigned int pcs : 1;
    621                 /** Device Mechanical Presence Status. */
    622                 unsigned int dmps : 1;
    623                 /** Reserved. */
    624                 unsigned int reserved1 : 14;
    625                 /** PhyRdy Change Status. */
    626                 unsigned int prcs : 1;
    627                 /** Incorrect Port Multiplier Status. */
    628                 unsigned int ipms : 1;
    629                 /** Overflow Status. */
    630                 unsigned int ofs : 1;
    631                 /** Reserved. */
    632                 unsigned int reserved2 : 1;
    633                 /** Interface Non-fatal Error Status. */
    634                 unsigned int infs : 1;
    635                 /** Interface Fatal Error Status. */
    636                 unsigned int ifs : 1;
    637                 /** Host Bus Data Error Status. */
    638                 unsigned int hbds : 1;
    639                 /** Host Bus Fatal Error Status. */
    640                 unsigned int hbfs : 1;
    641                 /** Task File Error Status. */
    642                 unsigned int tfes : 1;
    643                 /** Cold Port Detect Status. */
    644                 unsigned int cpds : 1;
    645         };
    646         uint32_t u32;
    647 } ahci_port_is_t;
     606typedef uint32_t ahci_port_is_t;
    648607
    649608#define AHCI_PORT_IS_DHRS  (1 << 0)
     
    700659static inline int ahci_port_is_end_of_operation(ahci_port_is_t port_is)
    701660{
    702         return port_is.u32 & AHCI_PORT_END_OF_OPERATION;
     661        return port_is & AHCI_PORT_END_OF_OPERATION;
    703662}
    704663
     
    712671static inline int ahci_port_is_error(ahci_port_is_t port_is)
    713672{
    714         return port_is.u32 & AHCI_PORT_IS_ERROR;
     673        return port_is & AHCI_PORT_IS_ERROR;
    715674}
    716675
     
    724683static inline int ahci_port_is_permanent_error(ahci_port_is_t port_is)
    725684{
    726         return port_is.u32 & AHCI_PORT_IS_PERMANENT_ERROR;
     685        return port_is & AHCI_PORT_IS_PERMANENT_ERROR;
    727686}
    728687
     
    736695static inline int ahci_port_is_tfes(ahci_port_is_t port_is)
    737696{
    738         return port_is.u32 & AHCI_PORT_IS_TFES;
     697        return port_is & AHCI_PORT_IS_TFES;
    739698}
    740699
     
    994953        uint32_t pxfbu;
    995954        /** Port x Interrupt Status. */
    996         uint32_t pxis;
     955        ahci_port_is_t pxis;
    997956        /** Port x Interrupt Enable. */
    998957        uint32_t pxie;
     
    1030989        ahci_ghc_t ghc;
    1031990        /** Reserved. */
    1032         uint32_t reserved[13]; 
     991        uint32_t reserved[13];
    1033992        /** Reserved for NVMHCI. */
    1034993        uint32_t reservedfornvmhci[16];
     
    1036995        uint32_t vendorspecificsregs[24];
    1037996        /** Ports. */
    1038         ahci_port_t ports[32];
     997        ahci_port_t ports[AHCI_MAX_PORTS];
    1039998} ahci_memregs_t;
    1040999
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