Changeset 7c3fb9b in mainline for uspace/drv/platform/amdm37x/amdm37x.c

Timestamp:

2018-05-17T08:29:01Z (6 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ff23ff

Parents:

fac0ac7

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)

Message:

Fix block comment formatting (ccheck).

File:

• uspace/drv/platform/amdm37x/amdm37x.c (modified) (10 diffs)

uspace/drv/platform/amdm37x/amdm37x.c

@@ -127 +127 @@
 {
         assert(device);
-        /* Get SYS_CLK value, it is used as reference clock by all DPLLs,
-         * NFI who sets this or why it is set to specific value. */
+        /*
+         * Get SYS_CLK value, it is used as reference clock by all DPLLs,
+         * NFI who sets this or why it is set to specific value.
+         */
         const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) &
             CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
@@ -138 +140 @@
 
 
-        /* DPLL1 provides MPU(CPU) clock.
+        /*
+         * DPLL1 provides MPU(CPU) clock.
          * It uses SYS_CLK as reference clock and core clock (DPLL3) as
          * high frequency bypass (MPU then runs on L3 interconnect freq).
-         * It should be setup by fw or u-boot.*/
+         * It should be setup by fw or u-boot.
+         */
         mpu_cm_regs_t *mpu = device->cm.mpu;
 
@@ -183 +187 @@
         // TODO: Enable this (automatic MPU downclocking):
 #if 0
-        /* Enable low power bypass mode, this will take effect the next lock or
-         * relock sequence. */
+        /*
+         * Enable low power bypass mode, this will take effect the next lock or
+         * relock sequence.
+         */
         //TODO: We might need to force re-lock after enabling this
         pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
@@ -191 +197 @@
 #endif
 
-        /* DPLL2 provides IVA(video acceleration) clock.
+        /*
+         * DPLL2 provides IVA(video acceleration) clock.
          * It uses SYS_CLK as reference clokc and core clock (DPLL3) as
          * high frequency bypass (IVA runs on L3 freq).
          */
         // TODO: We can probably turn this off entirely. IVA is left unused.
-        /* Enable low power bypass mode, this will take effect the next lock or
-         * relock sequence. */
+        /*
+         * Enable low power bypass mode, this will take effect the next lock or
+         * relock sequence.
+         */
         //TODO: We might need to force re-lock after enabling this
         pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5);
@@ -203 +212 @@
         pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5);
 
-        /* DPLL3 provides tons of clocks:
+        /*
+         * DPLL3 provides tons of clocks:
          * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK,
          * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency
@@ -252 +262 @@
             CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5);
 
-        /* DPLL4 provides peripheral domain clocks:
+        /*
+         * DPLL4 provides peripheral domain clocks:
          * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK.
          * It uses SYS_CLK as reference clock and low frequency bypass.
@@ -263 +274 @@
             CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5);
 
-        /* DPLL5 provide peripheral domain clocks: 120M_FCLK.
+        /*
+         * DPLL5 provide peripheral domain clocks: 120M_FCLK.
          * It uses SYS_CLK as reference clock and low frequency bypass.
          * 120M clock is used by HS USB and USB TLL.
@@ -271 +283 @@
             CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) !=
             CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) {
-                /* Compute divisors and multiplier
-                 * See AMDM37x TRM p. 300 for the formula */
+                /*
+                 * Compute divisors and multiplier
+                 * See AMDM37x TRM p. 300 for the formula
+                 */
                 // TODO: base_freq does not have to be rounded to Mhz
                 // (that's why I used KHz as unit).
@@ -383 +397 @@
             UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5);
 
-        /* Set all ports to go through TLL(UTMI)
-         * Direct connection can only work in HS mode */
+        /*
+         * Set all ports to go through TLL(UTMI)
+         * Direct connection can only work in HS mode
+         */
         pio_set_32(&device->uhh->hostconfig,
             UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG |
@@ -394 +410 @@
 
         for (unsigned i = 0; i < 3; ++i) {
-                /* Serial mode is the only one capable of FS/LS operation.
+                /*
+                 * Serial mode is the only one capable of FS/LS operation.
                  * Select FS/LS mode, no idea what the difference is
                  * one of bidirectional modes might be good choice
-                 * 2 = 3pin bidi phy. */
+                 * 2 = 3pin bidi phy.
+                 */
                 pio_change_32(&device->tll->channel_conf[i],
                     TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE |