Changeset 7c3fb9b in mainline for kernel/arch/arm32/src/cpu/cpu.c

Timestamp:

2018-05-17T08:29:01Z (6 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ff23ff

Parents:

fac0ac7

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)

Message:

Fix block comment formatting (ccheck).

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (2 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -147 +147 @@
         /* Unaligned access is supported on armv6+ */
 #if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
-        /* Enable unaligned access, RAZ/WI prior to armv6
+        /*
+         * Enable unaligned access, RAZ/WI prior to armv6
          * switchable on armv6, RAO/WI writes on armv7,
          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
-         * L.3.1 (p. 2456) */
+         * L.3.1 (p. 2456)
+         */
         control_reg |= SCTLR_UNALIGNED_EN_FLAG;
-        /* Disable alignment checks, this turns unaligned access to undefined,
-         * unless U bit is set. */
+        /*
+         * Disable alignment checks, this turns unaligned access to undefined,
+         * unless U bit is set.
+         */
         control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
-        /* Enable caching, On arm prior to armv7 there is only one level
+        /*
+         * Enable caching, On arm prior to armv7 there is only one level
          * of caches. Data cache is coherent.
          * "This means that the behavior of accesses from the same observer to
@@ -169 +174 @@
 #endif
 #ifdef PROCESSOR_ARCH_armv7_a
-        /* ICache coherency is elaborated on in barrier.h.
+        /*
+         * ICache coherency is elaborated on in barrier.h.
          * VIPT and PIPT caches need maintenance only on code modify,
          * so it should be safe for general use.