Changeset 7c3fb9b in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2018-05-17T08:29:01Z (6 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ff23ff

Parents:

fac0ac7

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)

Message:

Fix block comment formatting (ccheck).

File:

• boot/arch/arm32/src/mm.c (modified) (3 diffs)

boot/arch/arm32/src/mm.c

@@ -210 +210 @@
             "mrc p15, 0, r0, c1, c0, 0\n"
 
-            /* Enable ICache, DCache, BPredictors and MMU,
+            /*
+             * Enable ICache, DCache, BPredictors and MMU,
              * we disable caches before jumping to kernel
              * so this is safe for all archs.
@@ -224 +225 @@
             "orr r0, r0, r1\n"
 
-            /* Invalidate the TLB content before turning on the MMU.
+            /*
+             * Invalidate the TLB content before turning on the MMU.
              * ARMv7-A Reference manual, B3.10.3
              */
@@ -240 +242 @@
         disable_paging();
 #ifdef PROCESSOR_ARCH_armv7_a
-        /* Make sure we run in memory code when caches are enabled,
+        /*
+         * Make sure we run in memory code when caches are enabled,
          * make sure we read memory data too. This part is ARMv7 specific as
          * ARMv7 no longer invalidates caches on restart.
-         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
+         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263
+         */
         cache_invalidate();
 #endif