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Changeset 7a38962 in mainline


Ignore:
Timestamp:
2013-01-20T11:42:22Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
c8a5c8c
Parents:
9043e7e0
Message:

arm32: Replace cortex-a8 compile check with runtime cache type check.

Update comments.
Fix typos in cp15.h.

Location:
kernel/arch/arm32
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/cp15.h

    r9043e7e0 r7a38962  
    8383        CTR_I_MIN_LINE_SHIFT = 0,
    8484        CTR_L1I_POLICY_MASK = 0x0000c000,
    85         VTR_L1I_POLICY_AIVIVT = 0x00004000,
    86         VTR_L1I_POLICY_VIPT = 0x00008000,
     85        CTR_L1I_POLICY_AIVIVT = 0x00004000,
     86        CTR_L1I_POLICY_VIPT = 0x00008000,
    8787        CTR_L1I_POLICY_PIPT = 0x0000c000,
    8888        /* ARMv6 format */
  • kernel/arch/arm32/src/cpu/cpu.c

    r9043e7e0 r7a38962  
    151151         *    B3.11.1 (p. 1383)
    152152         * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
    153          * L2 Cache for armv7 was enabled in boot code.
     153         * L2 Cache for armv7 is enabled by default (i.e. controlled by
     154         * this flag).
    154155         */
    155156        control_reg |= SCTLR_CACHE_EN_FLAG;
    156157#endif
    157 #ifdef PROCESSOR_cortex_a8
     158#ifdef PROCESSOR_ARCH_armv7_a
    158159         /* ICache coherency is elaborate on in barrier.h.
    159           * Cortex-A8 implements IVIPT extension.
    160           * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
    161         control_reg |= SCTLR_INST_CACHE_EN_FLAG;
    162         /* Enable branch prediction RAZ/WI if not supported */
    163         control_reg |= SCTLR_BRANCH_PREDICT_EN_FLAG;
     160          * VIPT and PIPT caches need maintenance only on code modify,
     161          * so it should be safe for general use.
     162          * Enable branch predictors too as they follow the same rules
     163          * as ICache and they can be flushed together
     164          */
     165        if ((CTR_read() & CTR_L1I_POLICY_MASK) != CTR_L1I_POLICY_AIVIVT) {
     166                control_reg |=
     167                    SCTLR_INST_CACHE_EN_FLAG | SCTLR_BRANCH_PREDICT_EN_FLAG;
     168        }
    164169#endif
    165170        SCTLR_write(control_reg);
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