Changeset 7978d1e7 in mainline for uspace/drv/audio/hdaudio/spec/regs.h
- Timestamp:
- 2014-08-14T08:56:27Z (10 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8d070710
- Parents:
- b229062
- File:
-
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/audio/hdaudio/spec/regs.h
rb229062 r7978d1e7 33 33 */ 34 34 35 #ifndef HDAUDIO_REGS_H36 #define HDAUDIO_REGS_H35 #ifndef SPEC_REGS_H 36 #define SPEC_REGS_H 37 37 38 38 #include <sys/types.h> … … 100 100 uint32_t walclk; 101 101 /** Reserved */ 102 uint32_t reserved4[4]; 102 uint8_t reserved4[4]; 103 /** Stream Synchronization */ 104 uint32_t ssync; 105 /** Reserved */ 106 uint8_t reserved5[4]; 103 107 /** CORB Lower Base Address */ 104 108 uint32_t corblbase; … … 116 120 uint8_t corbsize; 117 121 /** Reserved */ 118 uint8_t reserved 5[1];122 uint8_t reserved6[1]; 119 123 /** RIRB Lower Base Address */ 120 124 uint32_t rirblbase; … … 132 136 uint8_t rirbsize; 133 137 /** Reserved */ 134 uint8_t reserved 6[1];138 uint8_t reserved7[1]; 135 139 /** Immediate Command Output Interface */ 136 140 uint32_t icoi; … … 140 144 uint32_t icis; 141 145 /** Reserved */ 142 uint8_t reserved 7[6];146 uint8_t reserved8[6]; 143 147 /** DMA Position Buffer Lower Base */ 144 148 uint32_t dpiblbase; … … 146 150 uint32_t dpibubase; 147 151 /** Reserved */ 148 uint8_t reserved 8[8];152 uint8_t reserved9[8]; 149 153 /** Stream descriptor registers */ 150 154 hda_sdesc_regs_t sdesc[64]; 151 155 /** Fill up to 0x2030 */ 152 uint8_t reserved 9[6064];156 uint8_t reserved10[6064]; 153 157 /** Wall Clock Counter Alias */ 154 158 uint32_t walclka; … … 157 161 } hda_regs_t; 158 162 163 typedef enum { 164 /** Number of Output Streams Supported (H) */ 165 gcap_oss_h = 15, 166 /** Number of Output Streams Supported (L) */ 167 gcap_oss_l = 12, 168 /** Number of Input Streams Supported (H) */ 169 gcap_iss_h = 11, 170 /** Number of Input Streams Supported (L) */ 171 gcap_iss_l = 8, 172 /** Number of Bidirectional Streams Supported (H) */ 173 gcap_bss_h = 7, 174 /** Number of Bidirectional Streams Supported (L) */ 175 gcap_bss_l = 3, 176 /** Number of Serial Data Out Signals (H) */ 177 gcap_nsdo_h = 2, 178 /** Number of Serial Data Out Signals (H) */ 179 gcap_nsdo_l = 1, 180 /** 64 Bit Address Supported */ 181 gcap_64ok = 0 182 } hda_gcap_bits_t; 183 184 typedef enum { 185 /** Accept Unsolicited Response Enable */ 186 gctl_unsol = 8, 187 /** Flush Control */ 188 gctl_fcntrl = 1, 189 /** Controller Reset */ 190 gctl_crst = 0 191 } hda_gctl_bits_t; 192 193 typedef enum { 194 /** CORB Read Pointer Reset */ 195 corbrp_rst = 15, 196 /** CORB Read Pointer (H) */ 197 corbrp_rp_h = 7, 198 /** CORB Read Pointer (L) */ 199 corbrp_rp_l = 0 200 } hda_corbrp_bits_t; 201 202 typedef enum { 203 /** Enable CORB DMA Engine */ 204 corbctl_run = 1, 205 /** CORB Memory Error Interrupt Enable */ 206 corbctl_meie = 0 207 } hda_corbctl_bits_t; 208 209 typedef enum { 210 /** CORB Size Capability (H) */ 211 corbsize_cap_h = 7, 212 /** CORB Size Capability (L) */ 213 corbsize_cap_l = 4, 214 /** CORB Size (H) */ 215 corbsize_size_h = 1, 216 /** CORB Size (L) */ 217 corbsize_size_l = 0 218 } hda_corbsize_bits_t; 219 220 typedef enum { 221 /** RIRB Write Pointer Reset */ 222 rirbwp_rst = 15, 223 /** RIRB Write Pointer (H) */ 224 rirbwp_wp_h = 7, 225 /** RIRB Write Pointer (L) */ 226 rirbrp_wp_l = 0 227 } hda_rirbwp_bits_t; 228 229 typedef enum { 230 /** Response Overrun Interrupt Control */ 231 rirbctl_oic = 2, 232 /** RIRB DMA Enable */ 233 rirbctl_run = 1, 234 /** CORB Memory Error Interrupt Enable */ 235 rirbctl_int = 0 236 } hda_rirbctl_bits_t; 237 238 typedef enum { 239 /** RIRB Size Capability (H) */ 240 rirbsize_cap_h = 7, 241 /** RIRB Size Capability (L) */ 242 rirbsize_cap_l = 4, 243 /** RIRB Size (H) */ 244 rirbsize_size_h = 1, 245 /** RIRB Size (L) */ 246 rirbsize_size_l = 0 247 } hda_rirbsize_bits_t; 248 159 249 #endif 160 250
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