Changeset 77ded647 in mainline


Ignore:
Timestamp:
2018-02-01T11:42:11Z (6 years ago)
Author:
Ondřej Hlavatý <aearsis@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3e6ff9a
Parents:
17d34a8
Message:

xhci: do not avoid 64-bit writes

Location:
uspace/drv/bus/usb/xhci
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/bus/usb/xhci/commands.c

    r17d34a8 r77ded647  
    242242        cr_set_state(cr, XHCI_CR_STATE_CLOSED);
    243243
    244         /* Some systems, inc. QEMU, need whole 64-bit qword to be written */
    245244        XHCI_REG_SET(hc->op_regs, XHCI_OP_CS, 1);
    246         XHCI_REG_SET(hc->op_regs, XHCI_OP_CRCR_HI, 0);
    247245
    248246        while (XHCI_REG_RD(hc->op_regs, XHCI_OP_CRR))
    … …  
    283281static void abort_command_ring(xhci_hc_t *hc)
    284282{
    285         /* Some systems, inc. QEMU, need whole 64-bit qword to be written */
    286283        XHCI_REG_SET(hc->op_regs, XHCI_OP_CA, 1);
    287         XHCI_REG_SET(hc->op_regs, XHCI_OP_CRCR_HI, 0);
    288284}
    289285

  • uspace/drv/bus/usb/xhci/debug.c

    r17d34a8 r77ded647  
    176176        DUMP_REG(hc->op_regs, XHCI_OP_CA);
    177177        DUMP_REG(hc->op_regs, XHCI_OP_CRR);
    178         DUMP_REG(hc->op_regs, XHCI_OP_CRCR_LO);
    179         DUMP_REG(hc->op_regs, XHCI_OP_CRCR_HI);
    180         DUMP_REG(hc->op_regs, XHCI_OP_DCBAAP_LO);
    181         DUMP_REG(hc->op_regs, XHCI_OP_DCBAAP_HI);
     178        DUMP_REG(hc->op_regs, XHCI_OP_CRCR);
     179        DUMP_REG(hc->op_regs, XHCI_OP_DCBAAP);
    182180        DUMP_REG(hc->rt_regs, XHCI_RT_MFINDEX);
    183181
    … …  
    188186        DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_IMC);
    189187        DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERSTSZ);
    190         DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERSTBA_LO);
    191         DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERSTBA_HI);
    192         DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERDP_LO);
    193         DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERDP_HI);
     188        DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERSTBA);
     189        DUMP_REG(&hc->rt_regs->ir[0], XHCI_INTR_ERDP);
    194190}
    195191

  • uspace/drv/bus/usb/xhci/hc.c

    r17d34a8 r77ded647  
    477477
    478478        uint64_t dcbaaptr = hc->dcbaa_dma.phys;
    479         XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_LO, LOWER32(dcbaaptr));
    480         XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP_HI, UPPER32(dcbaaptr));
     479        XHCI_REG_WR(hc->op_regs, XHCI_OP_DCBAAP, dcbaaptr);
    481480        XHCI_REG_WR(hc->op_regs, XHCI_OP_MAX_SLOTS_EN, hc->max_slots);
    482481
    483482        uintptr_t crcr;
    484483        xhci_trb_ring_reset_dequeue_state(&hc->cr.trb_ring, &crcr);
    485         XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_LO, LOWER32(crcr));
    486         XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR_HI, UPPER32(crcr));
     484        XHCI_REG_WR(hc->op_regs, XHCI_OP_CRCR, crcr);
    487485
    488486        XHCI_REG_SET(hc->op_regs, XHCI_OP_EWE, 1);
    … …  
    492490        xhci_interrupter_regs_t *intr0 = &hc->rt_regs->ir[0];
    493491        XHCI_REG_WR(intr0, XHCI_INTR_ERSTSZ, hc->event_ring.segment_count);
    494         uint64_t erdp = hc->event_ring.dequeue_ptr;
    495         XHCI_REG_WR(intr0, XHCI_INTR_ERDP_LO, LOWER32(erdp));
    496         XHCI_REG_WR(intr0, XHCI_INTR_ERDP_HI, UPPER32(erdp));
    497         uint64_t erstptr = hc->event_ring.erst.phys;
    498         XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_LO, LOWER32(erstptr));
    499         XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA_HI, UPPER32(erstptr));
     492        XHCI_REG_WR(intr0, XHCI_INTR_ERDP, hc->event_ring.dequeue_ptr);
     493        XHCI_REG_WR(intr0, XHCI_INTR_ERSTBA, hc->event_ring.erst.phys);
    500494
    501495        if (hc->base.irq_cap > 0) {
    … …  
    670664                }
    671665
    672                 uint64_t erdp = hc->event_ring.dequeue_ptr;
    673                 XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
    674                 XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
     666                XHCI_REG_WR(intr, XHCI_INTR_ERDP, hc->event_ring.dequeue_ptr);
    675667        }
    676668
    … …  
    679671        uint64_t erdp = hc->event_ring.dequeue_ptr;
    680672        erdp |= XHCI_REG_MASK(XHCI_INTR_ERDP_EHB);
    681         XHCI_REG_WR(intr, XHCI_INTR_ERDP_LO, LOWER32(erdp));
    682         XHCI_REG_WR(intr, XHCI_INTR_ERDP_HI, UPPER32(erdp));
     673        XHCI_REG_WR(intr, XHCI_INTR_ERDP, erdp);
    683674
    684675        usb_log_debug2("Event ring run finished.");

  • uspace/drv/bus/usb/xhci/hw_struct/regs.h

    r17d34a8 r77ded647  
    371371         * 64:6 - Command Ring Pointer
    372372         */
    373         ioport32_t crcr_lo;
    374         ioport32_t crcr_hi;
     373        ioport64_t crcr;
    375374
    376375        PADD32[4];
    377376
    378         ioport32_t dcbaap_lo;
    379         ioport32_t dcbaap_hi;
     377        ioport64_t dcbaap;
    380378
    381379        /*
    … …  
    416414#define XHCI_OP_PAGESIZE      pagesize, 32, FIELD
    417415#define XHCI_OP_NOTIFICATION    dnctrl, 32, RANGE, 15, 0
    418 #define XHCI_OP_RCS            crcr_lo, 32,  FLAG, 0
    419 #define XHCI_OP_CS             crcr_lo, 32,  FLAG, 1
    420 #define XHCI_OP_CA             crcr_lo, 32,  FLAG, 2
    421 #define XHCI_OP_CRR            crcr_lo, 32,  FLAG, 3
     416#define XHCI_OP_RCS               crcr, 64,  FLAG, 0
     417#define XHCI_OP_CS                crcr, 64,  FLAG, 1
     418#define XHCI_OP_CA                crcr, 64,  FLAG, 2
     419#define XHCI_OP_CRR               crcr, 64,  FLAG, 3
    422420/*
    423421 * This shall be RANGE, 6, 0, but the value containing CR pointer and RCS flag
    424422 * must be written at once.
    425423 */
    426 #define XHCI_OP_CRCR_LO        crcr_lo, 32, FIELD
    427 #define XHCI_OP_CRCR_HI        crcr_hi, 32, FIELD
    428 #define XHCI_OP_DCBAAP_LO    dcbaap_lo, 32, FIELD
    429 #define XHCI_OP_DCBAAP_HI    dcbaap_hi, 32, FIELD
     424#define XHCI_OP_CRCR              crcr, 64, FIELD
     425#define XHCI_OP_DCBAAP          dcbaap, 64, FIELD
    430426#define XHCI_OP_MAX_SLOTS_EN    config, 32, RANGE, 7, 0
    431427#define XHCI_OP_U3E             config, 32,  FLAG, 8
    … …  
    458454        PADD32;
    459455
    460         ioport32_t erstba_lo;
    461         ioport32_t erstba_hi;
     456        ioport64_t erstba;
    462457
    463458        /*
    … …  
    466461         * 63:4 - Event Ring Dequeue Pointer
    467462         */
    468         ioport32_t erdp_lo;
    469         ioport32_t erdp_hi;
     463        ioport64_t erdp;
    470464} xhci_interrupter_regs_t;
    471465
    … …  
    475469#define XHCI_INTR_IMC             imod, 32, RANGE, 31, 16
    476470#define XHCI_INTR_ERSTSZ        erstsz, 32, FIELD
    477 #define XHCI_INTR_ERSTBA_LO  erstba_lo, 32, FIELD
    478 #define XHCI_INTR_ERSTBA_HI  erstba_hi, 32, FIELD
    479 #define XHCI_INTR_ERDP_ESI     erdp_lo, 32, RANGE,  2, 0
    480 #define XHCI_INTR_ERDP_EHB     erdp_lo, 32,  FLAG,  3
    481 #define XHCI_INTR_ERDP_LO      erdp_lo, 32, FIELD
    482 #define XHCI_INTR_ERDP_HI      erdp_hi, 32, FIELD
     471#define XHCI_INTR_ERSTBA        erstba, 64, FIELD
     472#define XHCI_INTR_ERDP_ESI        erdp, 64, RANGE,  2, 0
     473#define XHCI_INTR_ERDP_EHB        erdp, 64,  FLAG,  3
     474#define XHCI_INTR_ERDP            erdp, 64, FIELD
    483475
    484476/**
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