Changeset 7715994 in mainline for uspace/srv/net/netif/dp8390/ne2000.c


Ignore:
Timestamp:
2010-03-13T12:17:02Z (14 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
6ba20a6b
Parents:
d0febca (diff), 2070570 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/srv/net/netif/dp8390/ne2000.c

    rd0febca r7715994  
    7070 *  @param[in] millis The number of milliseconds to sleep.
    7171 */
    72 #define milli_delay( millis )   usleep(( millis ) * 1000 )
     72#define milli_delay(millis)     usleep((millis) * 1000)
    7373
    7474/** Type definition of the testing function.
    7575 */
    76 _PROTOTYPE( typedef int (*testf_t), (dpeth_t *dep, int pos, u8_t *pat)  );
     76_PROTOTYPE(typedef int (*testf_t), (dpeth_t *dep, int pos, u8_t *pat)   );
    7777
    7878/** First data pattern.
    7979 */
    80 u8_t    pat0[]= { 0x00, 0x00, 0x00, 0x00 };
     80u8_t    pat0[]= {0x00, 0x00, 0x00, 0x00};
    8181
    8282/** Second data pattern.
    8383 */
    84 u8_t    pat1[]= { 0xFF, 0xFF, 0xFF, 0xFF };
     84u8_t    pat1[]= {0xFF, 0xFF, 0xFF, 0xFF};
    8585
    8686/** Third data pattern.
    8787 */
    88 u8_t    pat2[]= { 0xA5, 0x5A, 0x69, 0x96 };
     88u8_t    pat2[]= {0xA5, 0x5A, 0x69, 0x96};
    8989
    9090/** Fourth data pattern.
    9191 */
    92 u8_t    pat3[]= { 0x96, 0x69, 0x5A, 0xA5 };
     92u8_t    pat3[]= {0x96, 0x69, 0x5A, 0xA5};
    9393
    9494/** Tests 8 bit NE2000 network interface.
     
    114114 */
    115115static void ne_stop(dpeth_t *dep);
    116 //_PROTOTYPE( static void milli_delay, (unsigned long millis)           );
     116//_PROTOTYPE(static void milli_delay, (unsigned long millis)            );
    117117
    118118/** Initializes the NE2000 network interface.
     
    150150                /* Reset the dp8390 */
    151151                outb_reg0(dep, DP_CR, CR_STP | CR_DM_ABORT);
    152                 for (i= 0; i < 0x1000 && ((inb_reg0(dep, DP_ISR) & ISR_RST) == 0); i++)
     152                for (i= 0; i < 0x1000 && ((inb_reg0(dep, DP_ISR) &ISR_RST) == 0); i++)
    153153                        ; /* Do nothing */
    154154
    155155                /* Check if the dp8390 is really there */
    156                 if ((inb_reg0(dep, DP_CR) & (CR_STP|CR_DM_ABORT)) !=
     156                if ((inb_reg0(dep, DP_CR) &(CR_STP|CR_DM_ABORT)) !=
    157157                        (CR_STP|CR_DM_ABORT))
    158158                {
     
    186186                        f= test_8;
    187187                }
    188                 if (f(dep, loc1, pat0) && f(dep, loc1, pat1) &&
    189                         f(dep, loc1, pat2) && f(dep, loc1, pat3) &&
    190                         f(dep, loc2, pat0) && f(dep, loc2, pat1) &&
     188                if (f(dep, loc1, pat0) && f(dep, loc1, pat1) && 
     189                        f(dep, loc1, pat2) && f(dep, loc1, pat3) && 
     190                        f(dep, loc2, pat0) && f(dep, loc2, pat1) && 
    191191                        f(dep, loc2, pat2) && f(dep, loc2, pat3))
    192192                {
     
    297297        outb_reg0(dep, DP_RBCR0, 4);
    298298        outb_reg0(dep, DP_RBCR1, 0);
    299         outb_reg0(dep, DP_RSAR0, pos & 0xFF);
     299        outb_reg0(dep, DP_RSAR0, pos &0xFF);
    300300        outb_reg0(dep, DP_RSAR1, pos >> 8);
    301301        outb_reg0(dep, DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
     
    306306        for (i= 0; i<N; i++)
    307307        {
    308                 if (inb_reg0(dep, DP_ISR) & ISR_RDC)
     308                if (inb_reg0(dep, DP_ISR) &ISR_RDC)
    309309                        break;
    310310        }
     
    321321        outb_reg0(dep, DP_RBCR0, 4);
    322322        outb_reg0(dep, DP_RBCR1, 0);
    323         outb_reg0(dep, DP_RSAR0, pos & 0xFF);
     323        outb_reg0(dep, DP_RSAR0, pos &0xFF);
    324324        outb_reg0(dep, DP_RSAR1, pos >> 8);
    325325        outb_reg0(dep, DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
     
    349349        outb_reg0(dep, DP_RBCR0, 4);
    350350        outb_reg0(dep, DP_RBCR1, 0);
    351         outb_reg0(dep, DP_RSAR0, pos & 0xFF);
     351        outb_reg0(dep, DP_RSAR0, pos &0xFF);
    352352        outb_reg0(dep, DP_RSAR1, pos >> 8);
    353353        outb_reg0(dep, DP_CR, CR_DM_RW | CR_PS_P0 | CR_STA);
     
    360360        for (i= 0; i<N; i++)
    361361        {
    362                 if (inb_reg0(dep, DP_ISR) & ISR_RDC)
     362                if (inb_reg0(dep, DP_ISR) &ISR_RDC)
    363363                        break;
    364364        }
     
    375375        outb_reg0(dep, DP_RBCR0, 4);
    376376        outb_reg0(dep, DP_RBCR1, 0);
    377         outb_reg0(dep, DP_RSAR0, pos & 0xFF);
     377        outb_reg0(dep, DP_RSAR0, pos &0xFF);
    378378        outb_reg0(dep, DP_RSAR1, pos >> 8);
    379379        outb_reg0(dep, DP_CR, CR_DM_RR | CR_PS_P0 | CR_STA);
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