Index: uspace/drv/block/ahci/ahci.c
===================================================================
--- uspace/drv/block/ahci/ahci.c	(revision a00d5556cec82c86f4b79c6098d66b715a903bb2)
+++ uspace/drv/block/ahci/ahci.c	(revision 730dce77253b6e2ff27c35fa1c5ddc07e8cfe838)
@@ -601,5 +601,5 @@
 	if ((sata->invalid_device) || (ahci_port_is_error(pxis))) {
 		ddf_msg(LVL_ERROR,
-		    "%s: Unrecoverable error during fpdma write", sata->model);
+		    "%s: Unrecoverable error during FPDMA write", sata->model);
 		return EINTR;
 	}
Index: uspace/drv/block/ahci/ahci_hw.h
===================================================================
--- uspace/drv/block/ahci/ahci_hw.h	(revision a00d5556cec82c86f4b79c6098d66b715a903bb2)
+++ uspace/drv/block/ahci/ahci_hw.h	(revision 730dce77253b6e2ff27c35fa1c5ddc07e8cfe838)
@@ -89,5 +89,5 @@
 	/** Indicates what device number assigned by the vendor */
 	uint16_t deviceid;
-} __attribute__((packed)) ahci_pcireg_id_t;
+} ahci_pcireg_id_t;
 
 /** AHCI PCI register Command. */
@@ -120,7 +120,7 @@
 		/** Reserved. */
 		unsigned int reserved : 5;
-	} __attribute__((packed));
+	};
 	uint16_t u16;
-} __attribute__((packed)) ahci_pcireg_cmd_t;
+} ahci_pcireg_cmd_t;
 
 /** AHCI PCI register Command - Interrupt Disable bit. */
@@ -159,7 +159,7 @@
 		/** Detected parity error. */
 		unsigned int dpe : 1;
-	} __attribute__((packed));
+	};
 	uint16_t u16;
-} __attribute__((packed)) ahci_pcireg_sts_t;
+} ahci_pcireg_sts_t;
 
 /** AHCI PCI register Revision ID. */
@@ -167,5 +167,5 @@
 	/** Indicates stepping of the HBA hardware. */
 	uint8_t u8;
-} __attribute__((packed)) ahci_pcireg_rid_t;
+} ahci_pcireg_rid_t;
 
 /** AHCI PCI register Class Codes. */
@@ -179,11 +179,11 @@
 	/** Value 01 indicates that is a mass storage device. */
 	uint8_t bcc;
-} __attribute__((packed)) ahci_pcireg_cc_t_t;
+} ahci_pcireg_cc_t_t;
 
 /** AHCI PCI register Cache Line Size. */
 typedef struct {
-	/** Cache line sizefor use with the memory write and invalidate command. */
+	/** Cache line size for use with the memory write and invalidate command. */
 	uint8_t u8;
-} __attribute__((packed)) ahci_pcireg_cls_t;
+} ahci_pcireg_cls_t;
 
 /** AHCI PCI register Master Latency Timer. */
@@ -193,5 +193,5 @@
 	 */
 	uint8_t u8;
-} __attribute__((packed)) ahci_pcireg_mlt_t;
+} ahci_pcireg_mlt_t;
 
 /** AHCI PCI register Header Type. */
@@ -202,7 +202,7 @@
 		/** Multi function device. */
 		unsigned int mfd : 1;
-	} __attribute__((packed));
+	};
 	uint8_t u8;
-} __attribute__((packed)) ahci_pciregs_htype_t;
+} ahci_pciregs_htype_t;
 
 /** AHCI PCI register Built in self test. */
@@ -221,7 +221,7 @@
 	/** BIST capable. */
 	unsigned int bc : 1;
-	}  __attribute__((packed));
+	};
 	uint8_t u8;
-} __attribute__((packed)) ahci_pciregs_bist_t;
+} ahci_pciregs_bist_t;
 
 /** AHCI PCI register AHCI Base Address <BAR 5>. */
@@ -240,7 +240,7 @@
 		/** Base address of registry memory space. */
 		unsigned int ba : 19;
-	}  __attribute__((packed));
-	uint32_t u32;
-}  __attribute__((packed)) ahci_pciregs_abar_t;
+	};
+	uint32_t u32;
+} ahci_pciregs_abar_t;
 
 /** AHCI PCI register Subsystem Identifiers. */
@@ -251,5 +251,5 @@
 	/** Sub system identifier. */
 	uint8_t ssid;
-} __attribute__((packed)) ahci_pcireg_ss_t;
+} ahci_pcireg_ss_t;
 
 /** AHCI PCI registers Expansion ROM Base Address. */
@@ -258,5 +258,5 @@
 	/** Indicates the base address of the HBA expansion ROM. */
 	uint32_t u32;
-} __attribute__((packed)) ahci_pcireg_erom_t;
+} ahci_pcireg_erom_t;
 
 /** AHCI PCI register Capabilities Pointer. */
@@ -265,5 +265,5 @@
 	/** Indicates the first capability pointer offset. */
 	uint8_t u8;
-} __attribute__((packed)) ahci_pcireg_cap_t;
+} ahci_pcireg_cap_t;
 
 /** AHCI PCI register Interrupt Information. */
@@ -276,5 +276,5 @@
 	/** This indicates the interrupt pin the HBA uses. */
 	uint8_t ipin;
-} __attribute__((packed)) ahci_pcireg_intr;
+} ahci_pcireg_intr;
 
 /** AHCI PCI register Min Grant (Optional). */
@@ -285,5 +285,5 @@
 	 */
 	uint8_t u8;
-} __attribute__((packed)) ahci_pcireg_mgnt_t;
+} ahci_pcireg_mgnt_t;
 
 /** AHCI PCI register Max Latency (Optional). */
@@ -292,5 +292,5 @@
 	/** Indicates the maximum latency that the device can withstand. */
 	uint8_t u8;
-} __attribute__((packed)) ahci_pcireg_mlat_t;
+} ahci_pcireg_mlat_t;
 
 /*----------------------------------------------------------------------------*/
@@ -343,7 +343,7 @@
 		/** Supports 64-bit Addressing. */
 		unsigned int s64a : 1;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_cap_t;
+	};
+	uint32_t u32;
+} ahci_ghc_cap_t;
 
 /** AHCI Memory register Generic Host Control Global Host Control. */
@@ -360,7 +360,7 @@
 		/** AHCI Enable. */
 		unsigned int ae : 1;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_ghc_t;
+	};
+	uint32_t u32;
+} ahci_ghc_ghc_t;
 
 /** AHCI Enable mask bit. */
@@ -376,5 +376,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_is_t;
+} ahci_ghc_is_t;
 
 /** AHCI Memory register Ports implemented. */
@@ -384,5 +384,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_pi_t;
+} ahci_ghc_pi_t;
 
 /** AHCI Memory register AHCI version. */
@@ -392,5 +392,5 @@
 	/** Indicates the major version */
 	uint16_t mjr;
-} __attribute__((packed)) ahci_ghc_vs_t;
+} ahci_ghc_vs_t;
 
 /** AHCI Memory register Command completion coalesce control. */
@@ -409,7 +409,7 @@
 		/** Timeout value in  ms. */
 		uint16_t tv;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_ccc_ctl_t;
+	};
+	uint32_t u32;
+} ahci_ghc_ccc_ctl_t;
 
 /** AHCI Memory register Command completion coalescing ports. */
@@ -420,5 +420,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_ccc_ports_t;
+} ahci_ghc_ccc_ports_t;
 
 /** AHCI Memory register Enclosure management location. */
@@ -431,5 +431,5 @@
 	 */
 	uint16_t ofst;
-} __attribute__((packed)) ahci_ghc_em_loc;
+} ahci_ghc_em_loc;
 
 /** AHCI Memory register Enclosure management control. */
@@ -466,7 +466,7 @@
 		/** Reserved. */
 		unsigned int reserved4 : 4;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_em_ctl_t;
+	};
+	uint32_t u32;
+} ahci_ghc_em_ctl_t;
 
 /** AHCI Memory register HBA capatibilities extended. */
@@ -483,7 +483,7 @@
 		/** Reserved. */
 		unsigned int reserved : 29;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_cap2_t;
+	};
+	uint32_t u32;
+} ahci_ghc_cap2_t;
 
 /** AHCI Memory register BIOS/OS Handoff control and status. */
@@ -502,7 +502,7 @@
 		/** Reserved. */
 		unsigned int reserved : 27;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_ghc_bohc_t;
+	};
+	uint32_t u32;
+} ahci_ghc_bohc_t;
 
 /** AHCI Memory register Generic Host Control. */
@@ -531,5 +531,5 @@
 	/** BIOS/OS Handoff Control and Status. */
 	uint32_t bohc;
-} __attribute__((packed)) ahci_ghc_t;
+} ahci_ghc_t;
 
 /** AHCI Memory register Port x Command List Base Address. */
@@ -545,7 +545,7 @@
 		 */
 		unsigned int clb : 22;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_clb_t;
+	};
+	uint32_t u32;
+} ahci_port_clb_t;
 
 /** AHCI Memory register Port x Command List Base Address Upper 32-Bits. */
@@ -557,5 +557,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_port_clbu_t;
+} ahci_port_clbu_t;
 
 /** AHCI Memory register Port x FIS Base Address. */
@@ -563,5 +563,5 @@
 	struct {
 		/** Reserved. */
-		uint8_t reserved;
+		unsigned int reserved : 8;
 		/** FIS Base Address (FB) - Indicates the 32-bit base physical address
 		 * for received FISes. The structure pointed to by this address range
@@ -572,7 +572,7 @@
 		 */
 		unsigned int fb : 24;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_fb_t;
+	};
+	uint32_t u32;
+} ahci_port_fb_t;
 
 /** AHCI Memory register Port x FIS Base Address Upper 32-Bits. */
@@ -583,5 +583,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_port_fbu_t;
+} ahci_port_fbu_t;
 
 /** AHCI Memory register Port x Interrupt Status. */
@@ -626,7 +626,7 @@
 		/** Cold Port Detect Status. */
 		unsigned int cpds : 1;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_is_t;
+	};
+	uint32_t u32;
+} ahci_port_is_t;
 
 #define AHCI_PORT_IS_DHRS  (1 << 0)
@@ -763,7 +763,7 @@
 		/** Cold Port Detect Enable. */
 		unsigned int cpde : 1;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_ie_t;
+	};
+	uint32_t u32;
+} ahci_port_ie_t;
 
 /** AHCI Memory register Port x Command and Status. */
@@ -826,7 +826,7 @@
 		 */
 		unsigned int icc : 4;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_cmd_t;
+	};
+	uint32_t u32;
+} ahci_port_cmd_t;
 
 /** AHCI Memory register Port x Task File Data. */
@@ -843,7 +843,7 @@
 		/** Reserved. */
 		uint16_t reserved;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_tfd_t;
+	};
+	uint32_t u32;
+} ahci_port_tfd_t;
 
 /** AHCI Memory register Port x Signature. */
@@ -858,7 +858,7 @@
 		/**  LBA High Register */
 		uint8_t lba_hr;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_sig_t;
+	};
+	uint32_t u32;
+} ahci_port_sig_t;
 
 /** AHCI Memory register Port x Serial ATA Status (SCR0: SStatus). */
@@ -873,7 +873,7 @@
 		/** Reserved. */
 		unsigned int reserved : 20;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_ssts_t;
+	};
+	uint32_t u32;
+} ahci_port_ssts_t;
 
 /** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */
@@ -888,7 +888,7 @@
 		/** Reserved. */
 		unsigned int reserved : 20;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_sctl_t;
+	};
+	uint32_t u32;
+} ahci_port_sctl_t;
 
 /** AHCI Memory register Port x Port x Serial ATA Error (SCR1: SError). */
@@ -904,5 +904,5 @@
 	 */
 	uint16_t diag;
-} __attribute__((packed)) ahci_port_serr_t;
+} ahci_port_serr_t;
 
 /** AHCI Memory register Port x Serial ATA Active (SCR3: SActive). */
@@ -913,5 +913,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_port_sact_t;
+} ahci_port_sact_t;
 
 /** AHCI Memory register Port x Command Issue. */
@@ -921,5 +921,5 @@
 	 */
 	uint32_t u32;
-} __attribute__((packed)) ahci_port_ci_t;
+} ahci_port_ci_t;
 
 /** AHCI Memory register Port x Serial ATA Notification
@@ -934,5 +934,5 @@
 	/** Reserved. */
 	uint16_t reserved;
-} __attribute__((packed)) ahci_port_sntf_t;
+} ahci_port_sntf_t;
 
 /** AHCI Memory register Port x FIS-based Switching Control.
@@ -958,7 +958,7 @@
 		/** Reserved. */
 		unsigned int reserved2 : 1;
-	} __attribute__((packed));
-	uint32_t u32;
-} __attribute__((packed)) ahci_port_fbs_t;
+	};
+	uint32_t u32;
+} ahci_port_fbs_t;
 
 /** AHCI Memory register Port. */
@@ -1003,5 +1003,5 @@
 	/** Port x Vendor Specific. */
 	uint32_t pxvs[4];
-} __attribute__((packed)) ahci_port_t;
+} ahci_port_t;
 
 /** AHCI Memory Registers. */
@@ -1017,5 +1017,5 @@
 	/** Ports. */
 	ahci_port_t ports[32];
-} __attribute__((packed)) ahci_memregs_t;
+} ahci_memregs_t;
 
 /** AHCI Command header entry. */
@@ -1031,5 +1031,5 @@
 	/** Command Table Descriptor Base Address Upper 32-bits. */
 	uint32_t cmdtableu;
-} __attribute__((packed)) ahci_cmdhdr_t;
+} ahci_cmdhdr_t;
 
 /** AHCI Command Physical Region Descriptor entry. */
@@ -1047,5 +1047,5 @@
 	/** Interrupt on completion */
 	unsigned int ioc : 1;
-} __attribute__((packed)) ahci_cmd_prdt_t;
+} ahci_cmd_prdt_t;
 
 #endif
Index: uspace/drv/block/ahci/ahci_sata.h
===================================================================
--- uspace/drv/block/ahci/ahci_sata.h	(revision a00d5556cec82c86f4b79c6098d66b715a903bb2)
+++ uspace/drv/block/ahci/ahci_sata.h	(revision 730dce77253b6e2ff27c35fa1c5ddc07e8cfe838)
@@ -39,28 +39,28 @@
 typedef struct {
 	/** FIS type - always 0x27. */
-	uint8_t fis_type;
+	unsigned int fis_type : 8;
 	/** Indicate that FIS is a Command - always 0x80. */
-	uint8_t c;
+	unsigned int c : 8;
 	/** Command - Identity device - 0xec, Set fetures - 0xef. */
-	uint8_t command;
+	unsigned int command : 8;
 	/** Features - subcommand for set features - set tranfer mode - 0x03. */
-	uint8_t features;
+	unsigned int features : 8;
 	/** 0:23 bits of LBA. */
-	uint32_t lba_lower : 24;
+	unsigned int lba_lower : 24;
 	/** Device. */
-	uint8_t device;
+	unsigned int device : 8;
 	/** 24:47 bits of LBA. */
-	uint32_t lba_upper : 24;
+	unsigned int lba_upper : 24;
 	/** Features - subcommand for set features - set tranfer mode - 0x03. */
-	uint8_t features_upper;
+	unsigned int features_upper : 8;
 	/** Sector count - transfer mode for set transfer mode operation. */
-	uint16_t count;
-	/** Reserved. */
-	uint8_t reserved1;
+	unsigned int count : 16;
+	/** Reserved. */
+	unsigned int reserved1 : 8;
 	/** Control. */
-	uint8_t control;
-	/** Reserved. */
-	uint32_t reserved2;
-} __attribute__((packed)) std_command_frame_t;
+	unsigned int control : 8;
+	/** Reserved. */
+	unsigned int reserved2 : 32;
+} std_command_frame_t;
 
 /** Command frame for NCQ data operation. */
@@ -105,5 +105,5 @@
 	/** Reserved. */
 	uint8_t reserved6;
-} __attribute__((packed)) ncq_command_frame_t;
+} ncq_command_frame_t;
 
 /** Data returned from identify device and identify packet device command. */
@@ -187,5 +187,5 @@
 	uint16_t _vs128[1 + 159 - 128];
 	uint16_t reserved160[1 + 255 - 160];
-} __attribute__((packed)) identify_data_t;
+} identify_data_t;
 
 /** Capability bits for register device. */