Fork us on GitHub Follow us on Facebook Follow us on Twitter

Changeset 72e1d6eb in mainline


Ignore:
Timestamp:
2012-07-03T19:35:41Z (8 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
master
Children:
bb4c9fca
Parents:
0bbd13e (diff), e943ecf (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge from lp:~jakub/helenos/mm.

Location:
kernel
Files:
13 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/abs32le/include/mm/page.h

    r0bbd13e r72e1d6eb  
    105105        set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
    106106
     107/* Set PTE present bit accessors for each level. */
     108#define SET_PTL1_PRESENT_ARCH(ptl0, i)  \
     109        set_pt_present((pte_t *) (ptl0), (size_t) (i))
     110#define SET_PTL2_PRESENT_ARCH(ptl1, i)
     111#define SET_PTL3_PRESENT_ARCH(ptl2, i)
     112#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
     113        set_pt_present((pte_t *) (ptl3), (size_t) (i))
     114
    107115/* Macros for querying the last level entries. */
    108116#define PTE_VALID_ARCH(p) \
     
    173181}
    174182
     183NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
     184    WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH))
     185    REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)
     186{
     187        pte_t *p = &pt[i];
     188
     189        p->present = 1;
     190}
     191
    175192extern void page_arch_init(void);
    176193extern void page_fault(unsigned int, istate_t *);
  • kernel/arch/amd64/include/mm/page.h

    r0bbd13e r72e1d6eb  
    119119        set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
    120120
     121/* Set PTE present bit accessors for each level. */
     122#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
     123        set_pt_present((pte_t *) (ptl0), (size_t) (i))
     124#define SET_PTL2_PRESENT_ARCH(ptl1, i) \
     125        set_pt_present((pte_t *) (ptl1), (size_t) (i))
     126#define SET_PTL3_PRESENT_ARCH(ptl2, i) \
     127        set_pt_present((pte_t *) (ptl2), (size_t) (i))
     128#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
     129        set_pt_present((pte_t *) (ptl3), (size_t) (i))
     130
    121131/* Macros for querying the last-level PTE entries. */
    122132#define PTE_VALID_ARCH(p) \
     
    215225}
    216226
     227NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
     228{
     229        pte_t *p = &pt[i];
     230
     231        p->present = 1;
     232}
     233
    217234extern void page_arch_init(void);
    218235extern void page_fault(unsigned int, istate_t *);
  • kernel/arch/amd64/src/mm/page.c

    r0bbd13e r72e1d6eb  
    5757        uintptr_t cur;
    5858        unsigned int identity_flags =
    59             PAGE_CACHEABLE | PAGE_EXEC | PAGE_GLOBAL | PAGE_WRITE;
     59            PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ;
    6060               
    6161        page_mapping_operations = &pt_mapping_operations;
  • kernel/arch/arm32/include/mm/page.h

    r0bbd13e r72e1d6eb  
    4040#include <mm/mm.h>
    4141#include <arch/exception.h>
     42#include <arch/barrier.h>
    4243#include <trace.h>
    4344
     
    109110#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    110111        set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x))
     112
     113/* Set PTE present bit accessors for each level. */
     114#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
     115        set_pt_level0_present((pte_t *) (ptl0), (size_t) (i))
     116#define SET_PTL2_PRESENT_ARCH(ptl1, i)
     117#define SET_PTL3_PRESENT_ARCH(ptl2, i)
     118#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
     119        set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
    111120
    112121/* Macros for querying the last-level PTE entries. */
     
    267276}
    268277
     278NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
     279{
     280        pte_level0_t *p = &pt[i].l0;
     281
     282        p->should_be_zero = 0;
     283        write_barrier();
     284        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
     285}
    269286
    270287/** Sets flags of level 1 page table entry.
     
    283300        pte_level1_t *p = &pt[i].l1;
    284301       
    285         if (flags & PAGE_NOT_PRESENT) {
     302        if (flags & PAGE_NOT_PRESENT)
    286303                p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
    287                 p->access_permission_3 = 1;
    288         } else {
     304        else
    289305                p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
    290                 p->access_permission_3 = p->access_permission_0;
    291         }
    292306       
    293307        p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
     
    312326}
    313327
    314 
     328NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
     329{
     330        pte_level1_t *p = &pt[i].l1;
     331
     332        p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
     333}
     334       
    315335extern void page_arch_init(void);
    316336
    317 
    318337#endif /* __ASM__ */
    319338
  • kernel/arch/ia32/include/mm/page.h

    r0bbd13e r72e1d6eb  
    115115        set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
    116116
     117/* Set PTE present bit accessors for each level. */
     118#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
     119        set_pt_present((pte_t *) (ptl0), (size_t) (i))
     120#define SET_PTL2_PRESENT_ARCH(ptl1, i)
     121#define SET_PTL3_PRESENT_ARCH(ptl2, i)
     122#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
     123        set_pt_present((pte_t *) (ptl3), (size_t) (i))
     124
    117125/* Macros for querying the last level entries. */
    118126#define PTE_VALID_ARCH(p) \
     
    194202}
    195203
     204NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
     205{
     206        pte_t *p = &pt[i];
     207
     208        p->present = 1;
     209}
     210
    196211extern void page_arch_init(void);
    197212extern void page_fault(unsigned int, istate_t *);
  • kernel/arch/ia32/src/mm/page.c

    r0bbd13e r72e1d6eb  
    7171        for (cur = 0; cur < min(config.identity_size, config.physmem_end);
    7272            cur += FRAME_SIZE) {
    73                 flags = PAGE_CACHEABLE | PAGE_WRITE;
    74                 if ((PA2KA(cur) >= config.base) &&
    75                     (PA2KA(cur) < config.base + config.kernel_size))
    76                         flags |= PAGE_GLOBAL;
     73                flags = PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_WRITE | PAGE_READ;
    7774                page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
    7875        }
  • kernel/arch/mips32/include/mm/page.h

    r0bbd13e r72e1d6eb  
    128128        set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
    129129
     130/* Set PTE present bit accessors for each level. */
     131#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
     132        set_pt_present((pte_t *) (ptl0), (size_t) (i))
     133#define SET_PTL2_PRESENT_ARCH(ptl1, i)
     134#define SET_PTL3_PRESENT_ARCH(ptl2, i)
     135#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
     136        set_pt_present((pte_t *) (ptl3), (size_t) (i))
     137
    130138/* Last-level info macros. */
    131139#define PTE_VALID_ARCH(pte)                     (*((uint32_t *) (pte)) != 0)
     
    182190}
    183191
     192NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
     193{
     194        pte_t *p = &pt[i];
     195
     196        p->p = 1;
     197}
     198       
     199
    184200extern void page_arch_init(void);
    185201
  • kernel/arch/ppc32/include/mm/page.h

    r0bbd13e r72e1d6eb  
    128128#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    129129        set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x))
     130
     131/* Set PTE present accessors for each level. */
     132#define SET_PTL1_PRESENT_ARCH(ptl0, i) \
     133        set_pt_present((pte_t *) (ptl0), (size_t) (i))
     134
     135#define SET_PTL2_PRESENT_ARCH(ptl1, i)
     136#define SET_PTL3_PRESENT_ARCH(ptl2, i)
     137
     138#define SET_FRAME_PRESENT_ARCH(ptl3, i) \
     139        set_pt_present((pte_t *) (ptl3), (size_t) (i))
    130140
    131141/* Macros for querying the last-level PTEs. */
     
    175185}
    176186
     187NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
     188{
     189        pte_t *entry = &pt[i];
     190
     191        entry->present = 1;
     192}
     193
    177194extern void page_arch_init(void);
    178195
  • kernel/genarch/include/mm/page_pt.h

    r0bbd13e r72e1d6eb  
    115115
    116116/*
     117 * These macros are provided to set the present bit within the page tables.
     118 *
     119 */
     120#define SET_PTL1_PRESENT(ptl0, i)   SET_PTL1_PRESENT_ARCH(ptl0, i)
     121#define SET_PTL2_PRESENT(ptl1, i)   SET_PTL2_PRESENT_ARCH(ptl1, i)
     122#define SET_PTL3_PRESENT(ptl2, i)   SET_PTL3_PRESENT_ARCH(ptl2, i)
     123#define SET_FRAME_PRESENT(ptl3, i)  SET_FRAME_PRESENT_ARCH(ptl3, i)
     124
     125/*
    117126 * Macros for querying the last-level PTEs.
    118127 *
  • kernel/genarch/src/mm/page_ht.c

    r0bbd13e r72e1d6eb  
    4545#include <typedefs.h>
    4646#include <arch/asm.h>
     47#include <arch/barrier.h>
    4748#include <synch/spinlock.h>
    4849#include <arch.h>
     
    207208                pte->page = ALIGN_DOWN(page, PAGE_SIZE);
    208209                pte->frame = ALIGN_DOWN(frame, FRAME_SIZE);
     210
     211                write_barrier();
    209212               
    210213                hash_table_insert(&page_ht, key, &pte->link);
  • kernel/genarch/src/mm/page_pt.c

    r0bbd13e r72e1d6eb  
    4343#include <arch/mm/page.h>
    4444#include <arch/mm/as.h>
     45#include <arch/barrier.h>
    4546#include <typedefs.h>
    4647#include <arch/asm.h>
     
    8687                SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt));
    8788                SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page),
    88                     PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
     89                    PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
    8990                    PAGE_WRITE);
     91                write_barrier();
     92                SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page));
    9093        }
    9194       
     
    98101                SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt));
    99102                SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page),
    100                     PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
     103                    PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
    101104                    PAGE_WRITE);
     105                write_barrier();
     106                SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));       
    102107        }
    103108       
     
    110115                SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt));
    111116                SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page),
    112                     PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
     117                    PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
    113118                    PAGE_WRITE);
     119                write_barrier();
     120                SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page));
    114121        }
    115122       
     
    117124       
    118125        SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame);
    119         SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags);
     126        SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT);
     127        write_barrier();
     128        SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page));
    120129}
    121130
     
    279288        if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT)
    280289                return NULL;
     290
     291        read_barrier();
    281292       
    282293        pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
    283294        if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT)
    284295                return NULL;
     296
     297#if (PTL1_ENTRIES != 0)
     298        read_barrier();
     299#endif
    285300       
    286301        pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
    287302        if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT)
    288303                return NULL;
     304
     305#if (PTL2_ENTRIES != 0)
     306        read_barrier();
     307#endif
    289308       
    290309        pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
     
    346365                SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(addr), KA2PA(l1));
    347366                SET_PTL1_FLAGS(ptl0, PTL0_INDEX(addr),
    348                     PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
    349                     PAGE_WRITE);
     367                    PAGE_PRESENT | PAGE_USER | PAGE_CACHEABLE |
     368                    PAGE_EXEC | PAGE_WRITE | PAGE_READ);
    350369        }
    351370}
  • kernel/generic/src/mm/as.c

    r0bbd13e r72e1d6eb  
    665665               
    666666                page_table_lock(as, false);
    667                
    668                 /*
    669                  * Start TLB shootdown sequence.
    670                  */
    671                 ipl_t ipl = tlb_shootdown_start(TLB_INVL_PAGES, as->asid,
    672                     area->base + P2SZ(pages), area->pages - pages);
    673667               
    674668                /*
     
    726720                                }
    727721                               
     722                                /*
     723                                 * Start TLB shootdown sequence.
     724                                 *
     725                                 * The sequence is rather short and can be
     726                                 * repeated multiple times. The reason is that
     727                                 * we don't want to have used_space_remove()
     728                                 * inside the sequence as it may use a blocking
     729                                 * memory allocation for its B+tree. Blocking
     730                                 * while holding the tlblock spinlock is
     731                                 * forbidden and would hit a kernel assertion.
     732                                 */
     733
     734                                ipl_t ipl = tlb_shootdown_start(TLB_INVL_PAGES,
     735                                    as->asid, area->base + P2SZ(pages),
     736                                    area->pages - pages);
     737               
    728738                                for (; i < size; i++) {
    729739                                        pte_t *pte = page_mapping_find(as,
     
    743753                                        page_mapping_remove(as, ptr + P2SZ(i));
    744754                                }
     755               
     756                                /*
     757                                 * Finish TLB shootdown sequence.
     758                                 */
     759               
     760                                tlb_invalidate_pages(as->asid,
     761                                    area->base + P2SZ(pages),
     762                                    area->pages - pages);
     763               
     764                                /*
     765                                 * Invalidate software translation caches
     766                                 * (e.g. TSB on sparc64, PHT on ppc32).
     767                                 */
     768                                as_invalidate_translation_cache(as,
     769                                    area->base + P2SZ(pages),
     770                                    area->pages - pages);
     771                                tlb_shootdown_finalize(ipl);
    745772                        }
    746773                }
    747                
    748                 /*
    749                  * Finish TLB shootdown sequence.
    750                  */
    751                
    752                 tlb_invalidate_pages(as->asid, area->base + P2SZ(pages),
    753                     area->pages - pages);
    754                
    755                 /*
    756                  * Invalidate software translation caches
    757                  * (e.g. TSB on sparc64, PHT on ppc32).
    758                  */
    759                 as_invalidate_translation_cache(as, area->base + P2SZ(pages),
    760                     area->pages - pages);
    761                 tlb_shootdown_finalize(ipl);
    762                
    763774                page_table_unlock(as, false);
    764775        } else {
  • kernel/generic/src/mm/tlb.c

    r0bbd13e r72e1d6eb  
    162162       
    163163        size_t i;
    164         for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) {
     164        for (i = 0; i < CPU->tlb_messages_count; i++) {
    165165                tlb_invalidate_type_t type = CPU->tlb_messages[i].type;
    166166                asid_t asid = CPU->tlb_messages[i].asid;
     
    188188        }
    189189       
     190        CPU->tlb_messages_count = 0;
    190191        irq_spinlock_unlock(&CPU->lock, false);
    191192        CPU->tlb_active = true;
Note: See TracChangeset for help on using the changeset viewer.