Ignore:
Timestamp:
2010-02-20T22:23:42Z (14 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
61001a9, af56e9b
Parents:
aa30c7f (diff), c2efbb4 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge from lp:~rimskyp/helenos/sparc.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/mm/sun4v/mmu.h

    raa30c7f r721d4e85  
    4545#define ASI_SECONDARY_CONTEXT_REG       0x21    /**< secondary context register ASI. */
    4646
    47 
    48 
    49 
    50 
    51 
    52 
    53 
    54 
    55 
    56 
    57 /* I-MMU ASIs. */
    58 #define ASI_IMMU                        0x50
    59 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    60 #define ASI_IMMU_TSB_64KB_PTR_REG       0x52
    61 #define ASI_ITLB_DATA_IN_REG            0x54
    62 #define ASI_ITLB_DATA_ACCESS_REG        0x55
    63 #define ASI_ITLB_TAG_READ_REG           0x56
    64 #define ASI_IMMU_DEMAP                  0x57
    65 
    66 /* Virtual Addresses within ASI_IMMU. */
    67 #define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
    68 #define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    69 #define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
    70 #define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    71 #if defined (US3)
    72 #define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
    73 #define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
    74 #endif
    75 
    76 
    77 /* D-MMU ASIs. */
    78 #define ASI_DMMU                        0x58
    79 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    80 #define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
    81 #define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
    82 #define ASI_DTLB_DATA_IN_REG            0x5c
    83 #define ASI_DTLB_DATA_ACCESS_REG        0x5d
    84 #define ASI_DTLB_TAG_READ_REG           0x5e
    85 #define ASI_DMMU_DEMAP                  0x5f
    86 
    87 /* Virtual Addresses within ASI_DMMU. */
    88 #define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
    89 #define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
    90 #define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
    91 #define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
    92 #define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
    93 #define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
    94 #define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
    95 #define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
    96 #define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
    97 #if defined (US3)
    98 #define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
    99 #define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
    100 #define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
    101 #endif
    102 
    103 #ifndef __ASM__
    104 
    105 #include <arch/asm.h>
    106 #include <arch/barrier.h>
    107 #include <arch/types.h>
    108 
    109 #if defined(US)
    110 /** LSU Control Register. */
    111 typedef union {
    112         uint64_t value;
    113         struct {
    114                 unsigned : 23;
    115                 unsigned pm : 8;
    116                 unsigned vm : 8;
    117                 unsigned pr : 1;
    118                 unsigned pw : 1;
    119                 unsigned vr : 1;
    120                 unsigned vw : 1;
    121                 unsigned : 1;
    122                 unsigned fm : 16;       
    123                 unsigned dm : 1;        /**< D-MMU enable. */
    124                 unsigned im : 1;        /**< I-MMU enable. */
    125                 unsigned dc : 1;        /**< D-Cache enable. */
    126                 unsigned ic : 1;        /**< I-Cache enable. */
    127                
    128         } __attribute__ ((packed));
    129 } lsu_cr_reg_t;
    130 #endif /* US */
    131 
    132 #endif /* !def __ASM__ */
    133 
    134 
    135 
    136 
    137 
    138 
    139 
    140 
    141 
    142 
    143 
    144 
    145 
    146 
    147 
    148 
    14947#endif
    15048
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