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Changeset 71ca5a4 in mainline


Ignore:
Timestamp:
2012-04-02T04:42:37Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
07a8ef5
Parents:
79e84c9
Message:

arm32: Add more SCTLR flag definitions.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/regutils.h

    r79e84c9 r71ca5a4  
    4141#define STATUS_REG_MODE_MASK         0x1f
    4242
     43#define CP15_R1_MMU_ENABLE_BIT       (1 << 0)
     44#define CP15_R1_ALIGNMENT_ENABLE_BIT (1 << 1)
     45#define CP15_R1_CACHE_ENABLE_BIT     (1 << 2)
     46#define CP15_R1_BRANCH_PREDICT_BIT   (1 << 11)
     47#define CP15_R1_INST_CACHE_BIT       (1 << 12)
    4348#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
     49#define CP15_R1_ROUND_ROBIN_BIT      (1 << 14)
     50#define CP15_R1_HA_ENABLE_BIT        (1 << 17)
     51#define CP15_R1_WXN_BIT              (1 << 19) /* Only if virt. supported */
     52#define CP15_R1_UWXN_BIT             (1 << 20) /* Only if virt. supported */
     53#define CP15_R1_FI_BIT               (1 << 21)
     54#define CP15_R1_VE_BIT               (1 << 24)
     55#define CP15_R1_EE_BIT               (1 << 25)
     56#define CP15_R1_NMFI_BIT             (1 << 27)
     57#define CP15_R1_TRE_BIT              (1 << 28)
     58#define CP15_R1_AFE_BIT              (1 << 29)
    4459
    4560/* ARM Processor Operation Modes */
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