Changeset 6ff23ff in mainline for kernel/arch/arm32/src/fpu_context.c
- Timestamp:
- 2018-05-17T13:46:56Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4f8772d4
- Parents:
- 7c3fb9b
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-16 18:44:36)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-17 13:46:56)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/fpu_context.c
r7c3fb9b r6ff23ff 117 117 static int fpu_have_coprocessor_access(void) 118 118 { 119 /*120 * The register containing the information (CPACR) is not available on armv6- 121 * rely on user decision to use CONFIG_FPU.122 */119 /* 120 * The register containing the information (CPACR) is not available 121 * on armv6-. Rely on user decision to use CONFIG_FPU. 122 */ 123 123 #ifdef PROCESSOR_ARCH_armv7_a 124 124 const uint32_t cpacr = CPACR_read(); 125 /* FPU needs access to coprocessor 10 and 11. 126 * Moreover they need to have same access enabled */ 125 /* 126 * FPU needs access to coprocessor 10 and 11. 127 * Moreover, they need to have same access enabled 128 */ 127 129 if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) && 128 130 ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) { … … 131 133 } 132 134 #endif 135 133 136 return 1; 134 137 } … … 147 150 static void fpu_enable_coprocessor_access(void) 148 151 { 149 /*150 * The register containing the information (CPACR) is not available on armv6- 151 * rely on user decision to use CONFIG_FPU.152 */152 /* 153 * The register containing the information (CPACR) is not available 154 * on armv6-. Rely on user decision to use CONFIG_FPU. 155 */ 153 156 #ifdef PROCESSOR_ARCH_armv7_a 154 157 /* Allow coprocessor access */ 155 158 uint32_t cpacr = CPACR_read(); 156 /* FPU needs access to coprocessor 10 and 11. 157 * Moreover, they need to have same access enabled */ 159 /* 160 * FPU needs access to coprocessor 10 and 11. 161 * Moreover, they need to have same access enabled 162 */ 158 163 cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11)); 159 164 cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11)); … … 172 177 fpexc_write(0); 173 178 fpu_enable(); 174 /* Mask all exception traps, 179 /* 180 * Mask all exception traps, 175 181 * The bits are RAZ/WI on archs that don't support fpu exc traps. 176 182 */
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