Changeset 6ff23ff in mainline for kernel/arch/arm32/src/fpu_context.c

Timestamp:

2018-05-17T13:46:56Z (6 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4f8772d4

Parents:

7c3fb9b

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 18:44:36)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 13:46:56)

Message:

More comment fixing (ccheck).

File:

• kernel/arch/arm32/src/fpu_context.c (modified) (4 diffs)

kernel/arch/arm32/src/fpu_context.c

@@ -117 +117 @@
 static int fpu_have_coprocessor_access(void)
 {
-/*
- * The register containing the information (CPACR) is not available on armv6-
- * rely on user decision to use CONFIG_FPU.
- */
+        /*
+         * The register containing the information (CPACR) is not available
+         * on armv6-. Rely on user decision to use CONFIG_FPU.
+         */
 #ifdef PROCESSOR_ARCH_armv7_a
         const uint32_t cpacr = CPACR_read();
-        /* FPU needs access to coprocessor 10 and 11.
-         * Moreover they need to have same access enabled */
+        /*
+         * FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled
+         */
         if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
             ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
@@ -131 +133 @@
         }
 #endif
+
         return 1;
 }
@@ -147 +150 @@
 static void fpu_enable_coprocessor_access(void)
 {
-/*
- * The register containing the information (CPACR) is not available on armv6-
- * rely on user decision to use CONFIG_FPU.
- */
+        /*
+         * The register containing the information (CPACR) is not available
+         * on armv6-. Rely on user decision to use CONFIG_FPU.
+         */
 #ifdef PROCESSOR_ARCH_armv7_a
         /* Allow coprocessor access */
         uint32_t cpacr = CPACR_read();
-        /* FPU needs access to coprocessor 10 and 11.
-         * Moreover, they need to have same access enabled */
+        /*
+         * FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled
+         */
         cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
         cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
@@ -172 +177 @@
         fpexc_write(0);
         fpu_enable();
-        /* Mask all exception traps,
+        /*
+         * Mask all exception traps,
          * The bits are RAZ/WI on archs that don't support fpu exc traps.
          */