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Changeset 6b3ee0c5 in mainline


Ignore:
Timestamp:
2012-04-03T04:14:46Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
712a10b
Parents:
4d02595
Message:

arm32,boot: Enable caches on armv7 only.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/mm.c

    r4d02595 r6b3ee0c5  
    105105                /* Behave as a client of domains */
    106106                "ldr r0, =0x55555555\n"
    107                 "mcr p15, 0, r0, c3, c0, 0\n" 
     107                "mcr p15, 0, r0, c3, c0, 0\n"
    108108               
     109#ifdef PROCESSOR_armv7
     110                /* Clean L2 cache */
     111                "mov r12, #0x1\n"   //set up to invalidate L2
     112                "smc #0\n"  //Call SMI monitor
     113               
     114                /* Read Auxiliary control register */
     115                "mrc p15, 0, r0, c1, c0, 1\n"
     116                /* Mask to enable L2 cache */
     117                "ldr r1, =0x00000002\n"
     118                "orr r0, r0, r1\n"
     119                /* Store Auxiliary control register */
     120                "mrc p15, 0, r0, c1, c0, 1\n"
     121#endif
    109122                /* Current settings */
    110123                "mrc p15, 0, r0, c1, c0, 0\n"
    111124               
     125#ifdef PROCESSOR_armv7
    112126                /* Mask to enable paging, alignment and caching */
    113127                "ldr r1, =0x00000007\n"
     128#else
     129                /* Mask to enable paging */
     130                "ldr r1, =0x00000001\n"
     131#endif
    114132                "orr r0, r0, r1\n"
    115133               
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