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Changeset 6a6ebde in mainline


Ignore:
Timestamp:
2013-01-09T19:36:04Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
467f0c0
Parents:
813b024
Message:

arm32: Add some cp15 register values.

Change MODE_ values to enum
Add hybervisor and monitor modes.
Add security extensions header.

Location:
kernel/arch/arm32
Files:
1 added
3 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/cp15.h

    r813b024 r6a6ebde  
    6262CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
    6363
     64enum {
     65        ID_PFR0_THUMBEE_MASK = 0xf << 12,
     66        ID_PFR0_THUMBEE = 0x1 << 12,
     67        ID_PFR0_JAZELLE_MASK = 0xf << 8,
     68        ID_PFR0_JAZELLE = 0x1 << 8,
     69        ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8,
     70        ID_PFR0_THUMB_MASK = 0xf << 4,
     71        ID_PFR0_THUMB = 0x1 << 4,
     72        ID_PFR0_THUMB2 = 0x3 << 4,
     73        ID_PFR0_ARM_MASK = 0xf << 0,
     74        ID_PFR0_ARM = 0x1 << 0,
     75};
    6476CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0);
     77
     78enum {
     79        ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16,
     80        ID_PFR1_GEN_TIMER_EXT = 0x1 << 16,
     81        ID_PFR1_VIRT_EXT_MASK = 0xf << 12,
     82        ID_PFR1_VIRT_EXT = 0x1 << 12,
     83        ID_PFR1_M_PROF_MASK = 0xf << 8,
     84        ID_PFR1_M_PROF_MODEL = 0x2 << 8,
     85        ID_PFR1_SEC_EXT_MASK = 0xf << 4,
     86        ID_PFR1_SEC_EXT = 0x1 << 4,
     87        ID_PFR1_SEC_EXT_RFR = 0x2 << 4,
     88        ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0,
     89        ID_PFR1_ARMV4_MODEL = 0x1 << 0,
     90};
    6591CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1);
    6692CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2);
     
    94120CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1);
    95121CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
     122
     123enum {
     124        CPACR_ASEDIS_FLAG = 1 << 31,
     125        CPACR_D32DIS_FLAG = 1 << 30,
     126        CPACR_TRCDIS_FLAG = 1 << 28,
     127#define CPACR_CP_MASK(cp) (0x3 << (cp * 2))
     128#define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2))
     129#define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2))
     130#define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2))
     131};
    96132CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2);
    97133CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
    98134
    99135/* Implemented as part of Security extensions */
     136enum {
     137        SCR_SIF_FLAG = 1 << 9,
     138        SCR_HCE_FLAG = 1 << 8,
     139        SCR_SCD_FLAG = 1 << 7,
     140        SCR_nET_FLAG = 1 << 6,
     141        SCR_AW_FLAG = 1 << 5,
     142        SCR_FW_FLAG = 1 << 4,
     143        SCR_EA_FLAG = 1 << 3,
     144        SCR_FIQ_FLAG = 1 << 2,
     145        SCR_IRQ_FLAG = 1 << 1,
     146        SCR_NS_FLAG = 1 << 0,
     147};
    100148CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0);
    101149CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
    102150CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1);
    103151CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
     152
     153enum {
     154        NSACR_NSTRCDIS_FLAG = 1 << 20,
     155        NSACR_RFR_FLAG = 1 << 19,
     156        NSACR_NSASEDIS = 1 << 15,
     157        NSACR_NSD32DIS = 1 << 14,
     158#define NSACR_CP_FLAG(cp) (1 << cp)
     159};
    104160CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2);
    105161CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);
  • kernel/arch/arm32/include/regutils.h

    r813b024 r6a6ebde  
    6666
    6767/* ARM Processor Operation Modes */
    68 #define USER_MODE        0x10
    69 #define FIQ_MODE         0x11
    70 #define IRQ_MODE         0x12
    71 #define SUPERVISOR_MODE  0x13
    72 #define ABORT_MODE       0x17
    73 #define UNDEFINED_MODE   0x1b
    74 #define SYSTEM_MODE      0x1f
    75 
     68enum {
     69        USER_MODE = 0x10,
     70        FIQ_MODE = 0x11,
     71        IRQ_MODE = 0x12,
     72        SUPERVISOR_MODE = 0x13,
     73        MONITOR_MODE = 0x16,
     74        ABORT_MODE = 0x17,
     75        HYPERVISOR_MODE = 0x1a,
     76        UNDEFINED_MODE = 0x1b,
     77        SYSTEM_MODE = 0x1f,
     78        MODE_MASK = 0x1f,
     79};
    7680/* [CS]PRS manipulation macros */
    7781#define GEN_STATUS_READ(nm, reg) \
  • kernel/arch/arm32/src/fpu_context.c

    r813b024 r6a6ebde  
    3737#include <arch.h>
    3838#include <arch/types.h>
     39#include <arch/security_ext.h>
    3940#include <cpu.h>
    4041
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