Changeset 66b628a in mainline for uspace/srv/hw/netif/dp8390/dp8390.h


Ignore:
Timestamp:
2011-01-06T23:23:53Z (13 years ago)
Author:
martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7922dea
Parents:
e3fe7df
Message:

further code simplification

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/srv/hw/netif/dp8390/dp8390.h

    re3fe7df r66b628a  
    8989
    9090/** Page 1, read/write */
    91 #define DP_PAR0         0x1     /* Physical Address Register 0      */
    92 #define DP_PAR1         0x2     /* Physical Address Register 1      */
    93 #define DP_PAR2         0x3     /* Physical Address Register 2      */
    94 #define DP_PAR3         0x4     /* Physical Address Register 3      */
    95 #define DP_PAR4         0x5     /* Physical Address Register 4      */
    96 #define DP_PAR5         0x6     /* Physical Address Register 5      */
    97 #define DP_CURR         0x7     /* Current Page Register            */
    98 #define DP_MAR0         0x8     /* Multicast Address Register 0      */
    99 #define DP_MAR1         0x9     /* Multicast Address Register 1      */
    100 #define DP_MAR2         0xA     /* Multicast Address Register 2      */
    101 #define DP_MAR3         0xB     /* Multicast Address Register 3      */
    102 #define DP_MAR4         0xC     /* Multicast Address Register 4      */
    103 #define DP_MAR5         0xD     /* Multicast Address Register 5      */
    104 #define DP_MAR6         0xE     /* Multicast Address Register 6      */
    105 #define DP_MAR7         0xF     /* Multicast Address Register 7      */
     91#define DP_PAR0  0x01  /**< Physical Address Register 0 */
     92#define DP_PAR1  0x02  /**< Physical Address Register 1 */
     93#define DP_PAR2  0x03  /**< Physical Address Register 2 */
     94#define DP_PAR3  0x04  /**< Physical Address Register 3 */
     95#define DP_PAR4  0x05  /**< Physical Address Register 4 */
     96#define DP_PAR5  0x06  /**< Physical Address Register 5 */
     97#define DP_CURR  0x07  /**< Current Page Register */
     98#define DP_MAR0  0x08  /**< Multicast Address Register 0 */
     99#define DP_MAR1  0x09  /**< Multicast Address Register 1 */
     100#define DP_MAR2  0x0a  /**< Multicast Address Register 2 */
     101#define DP_MAR3  0x0b  /**< Multicast Address Register 3 */
     102#define DP_MAR4  0x0c  /**< Multicast Address Register 4 */
     103#define DP_MAR5  0x0d  /**< Multicast Address Register 5 */
     104#define DP_MAR6  0x0e  /**< Multicast Address Register 6 */
     105#define DP_MAR7  0x0f  /**< Multicast Address Register 7 */
    106106
    107107/* Bits in dp_cr */
     
    271271        dp_initf_t de_initf;
    272272        dp_stopf_t de_stopf;
    273         char de_name[sizeof("dp8390#n")];
    274273       
    275274        /*
     
    300299       
    301300        /* Fields for internal use by the dp8390 driver. */
    302         int de_flags;
    303         int de_mode;
    304301        eth_stat_t de_stat;
    305302        dp_user2nicf_t de_user2nicf;
     
    308305       
    309306        /* Driver flags */
     307        bool up;
     308        bool enabled;
     309        bool stopped;
    310310        bool sending;
    311311        bool send_avail;
    312312} dpeth_t;
    313313
    314 #define DEF_PROMISC     0x040
    315 #define DEF_MULTI       0x080
    316 #define DEF_BROAD       0x100
    317 #define DEF_ENABLED     0x200
    318 #define DEF_STOPPED     0x400
    319 
    320 #define DEM_DISABLED  0x0
    321 #define DEM_ENABLED   0x2
    322 
    323314#endif
    324315
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