Changeset 663f41c4 in mainline for uspace/drv/pciintel/pci_regs.h
- Timestamp:
- 2010-10-23T10:56:44Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 5291411
- Parents:
- 49698fa
- File:
-
- 1 edited
-
uspace/drv/pciintel/pci_regs.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/pciintel/pci_regs.h
r49698fa r663f41c4 1 1 /* 2 * Copyright (c) 2010 Lenka Trochtova 2 * Copyright (c) 2010 Lenka Trochtova 3 3 * All rights reserved. 4 4 * … … 32 32 /** @file 33 33 */ 34 35 #ifndef PCI_REGS_H36 #define PCI_REGS_H37 34 38 // Header types 39 #define PCI_HEADER_TYPE_DEV 0 40 #define PCI_HEADER_TYPE_BRIDGE 1 41 #define PCI_HEADER_TYPE_CARDBUS 2 35 #ifndef PCI_REGS_H_ 36 #define PCI_REGS_H_ 42 37 43 // Header type 0 and 1 44 #define PCI_VENDOR_ID 0x00 45 #define PCI_DEVICE_ID 0x02 46 #define PCI_COMMAND 0x04 47 #define PCI_STATUS 0x06 48 #define PCI_REVISION_ID 0x08 49 #define PCI_PROG_IF 0x09 50 #define PCI_SUB_CLASS 0x0A 51 #define PCI_BASE_CLASS 0x0B 52 #define PCI_CACHE_LINE_SIZE 0x0C 53 #define PCI_LATENCY_TIMER 0x0D 54 #define PCI_HEADER_TYPE 0x0E 55 #define PCI_BIST 0x0F 38 /* Header types */ 39 #define PCI_HEADER_TYPE_DEV 0 40 #define PCI_HEADER_TYPE_BRIDGE 1 41 #define PCI_HEADER_TYPE_CARDBUS 2 56 42 57 #define PCI_BASE_ADDR_0 0x10 58 #define PCI_BASE_ADDR_1 0x14 43 /* Header type 0 and 1 */ 44 #define PCI_VENDOR_ID 0x00 45 #define PCI_DEVICE_ID 0x02 46 #define PCI_COMMAND 0x04 47 #define PCI_STATUS 0x06 48 #define PCI_REVISION_ID 0x08 49 #define PCI_PROG_IF 0x09 50 #define PCI_SUB_CLASS 0x0A 51 #define PCI_BASE_CLASS 0x0B 52 #define PCI_CACHE_LINE_SIZE 0x0C 53 #define PCI_LATENCY_TIMER 0x0D 54 #define PCI_HEADER_TYPE 0x0E 55 #define PCI_BIST 0x0F 59 56 60 // Header type 0 61 #define PCI_BASE_ADDR_2 0x18 62 #define PCI_BASE_ADDR_3 0x1B 63 #define PCI_BASE_ADDR_4 0x20 64 #define PCI_BASE_ADDR_5 0x24 57 #define PCI_BASE_ADDR_0 0x10 58 #define PCI_BASE_ADDR_1 0x14 65 59 66 #define PCI_CARDBUS_CIS_PTR 0x28 67 #define PCI_SUBSYSTEM_VENDOR_ID 0x2C 68 #define PCI_SUBSYSTEM_ID 0x2E 69 #define PCI_EXP_ROM_BASE 0x30 70 #define PCI_CAP_PTR 0x34 71 #define PCI_INT_LINE 0x3C 72 #define PCI_INT_PIN 0x3D 73 #define PCI_MIN_GNT 0x3E 74 #define PCI_MAX_LAT 0x3F 60 /* Header type 0 */ 61 #define PCI_BASE_ADDR_2 0x18 62 #define PCI_BASE_ADDR_3 0x1B 63 #define PCI_BASE_ADDR_4 0x20 64 #define PCI_BASE_ADDR_5 0x24 75 65 76 // Header type 1 77 #define PCI_BRIDGE_PRIM_BUS_NUM 0x18 78 #define PCI_BRIDGE_SEC_BUS_NUM 0x19 79 #define PCI_BRIDGE_SUBORD_BUS_NUM 0x1A 80 #define PCI_BRIDGE_SEC_LATENCY_TIMER 0x1B 81 #define PCI_BRIDGE_IO_BASE 0x1C 82 #define PCI_BRIDGE_IO_LIMIT 0x1D 83 #define PCI_BRIDGE_SEC_STATUS 0x1E 84 #define PCI_BRIDGE_MEMORY_BASE 0x20 85 #define PCI_BRIDGE_MEMORY_LIMIT 0x22 86 #define PCI_BRIDGE_PREF_MEMORY_BASE 0x24 66 #define PCI_CARDBUS_CIS_PTR 0x28 67 #define PCI_SUBSYSTEM_VENDOR_ID 0x2C 68 #define PCI_SUBSYSTEM_ID 0x2E 69 #define PCI_EXP_ROM_BASE 0x30 70 #define PCI_CAP_PTR 0x34 71 #define PCI_INT_LINE 0x3C 72 #define PCI_INT_PIN 0x3D 73 #define PCI_MIN_GNT 0x3E 74 #define PCI_MAX_LAT 0x3F 75 76 /* Header type 1 */ 77 #define PCI_BRIDGE_PRIM_BUS_NUM 0x18 78 #define PCI_BRIDGE_SEC_BUS_NUM 0x19 79 #define PCI_BRIDGE_SUBORD_BUS_NUM 0x1A 80 #define PCI_BRIDGE_SEC_LATENCY_TIMER 0x1B 81 #define PCI_BRIDGE_IO_BASE 0x1C 82 #define PCI_BRIDGE_IO_LIMIT 0x1D 83 #define PCI_BRIDGE_SEC_STATUS 0x1E 84 #define PCI_BRIDGE_MEMORY_BASE 0x20 85 #define PCI_BRIDGE_MEMORY_LIMIT 0x22 86 #define PCI_BRIDGE_PREF_MEMORY_BASE 0x24 87 87 #define PCI_BRIDGE_PREF_MEMORY_LIMIT 0x26 88 88 #define PCI_BRIDGE_PREF_MEMORY_BASE_UP 0x28 89 89 #define PCI_BRIDGE_PREF_MEMORY_LIMIT_UP 0x2C 90 #define PCI_BRIDGE_IO_BASE_UP 91 #define PCI_BRIDGE_IO_LIMIT_UP 92 #define PCI_BRIDGE_EXP_ROM_BASE 93 #define PCI_BRIDGE_INT_LINE 94 #define PCI_BRIDGE_INT_PIN 95 #define PCI_BRIDGE_CTL 90 #define PCI_BRIDGE_IO_BASE_UP 0x30 91 #define PCI_BRIDGE_IO_LIMIT_UP 0x32 92 #define PCI_BRIDGE_EXP_ROM_BASE 0x38 93 #define PCI_BRIDGE_INT_LINE 0x3C 94 #define PCI_BRIDGE_INT_PIN 0x3D 95 #define PCI_BRIDGE_CTL 0x3E 96 96 97 97 #endif 98 99 98 100 99 /**
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