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Changeset 5e53e02 in mainline


Ignore:
Timestamp:
2009-12-06T19:02:16Z (12 years ago)
Author:
Pavel Rimsky <pavel@…>
Branches:
lfn, master
Children:
77f65df
Parents:
ba50a34
Message:

Merged fast data access MMU miss & protecion handlers ⇒ the uspace tasks now print their init info to the console.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/sparc64/src/mm/sun4v/tlb.c

    rba50a34 r5e53e02  
    6060#endif
    6161
    62 //static void dtlb_pte_copy(pte_t *, size_t, bool);
     62void dtlb_pte_copy(pte_t *t, bool ro);
    6363static void itlb_pte_copy(pte_t *);
    6464static void do_fast_instruction_access_mmu_miss_fault(istate_t *, const char *);
    65 //static void do_fast_data_access_mmu_miss_fault(istate_t *, uint64_t,
    66 //    const char *);
    67 //static void do_fast_data_access_protection_fault(istate_t *,
    68 //    uint64_t, const char *);
     65void do_fast_data_access_mmu_miss_fault(istate_t *istate,
     66    uint64_t page_and_ctx, const char *str);
     67static void do_fast_data_access_protection_fault(istate_t *,
     68    uint64_t, const char *);
     69
     70/*
     71 * The assembly language routine passes a 64-bit parameter to the Data Access
     72 * MMU Miss and Data Access protection handlers, the parameter encapsulates
     73 * a virtual address of the faulting page and the faulting context. The most
     74 * significant 51 bits represent the VA of the faulting page and the least
     75 * significant 13 vits represent the faulting context. The following macros
     76 * extract the page and context out of the 64-bit parameter:
     77 */
     78
     79/* extracts the VA of the faulting page */
     80#define DMISS_ADDRESS(page_and_ctx)     (((page_and_ctx) >> 13) << 13)
     81
     82/* extracts the faulting context */
     83#define DMISS_CONTEXT(page_and_ctx)     ((page_and_ctx) & 0x1fff)
    6984
    7085char *context_encoding[] = {
     
    132147}
    133148
    134 #if 0
    135149/** Copy PTE to TLB.
    136150 *
    137151 * @param t             Page Table Entry to be copied.
    138  * @param index         Zero if lower 8K-subpage, one if higher 8K-subpage.
    139152 * @param ro            If true, the entry will be created read-only, regardless
    140153 *                      of its w field.
    141154 */
    142 void dtlb_pte_copy(pte_t *t, size_t index, bool ro)
    143 {
    144         tlb_tag_access_reg_t tag;
    145         tlb_data_t data;
    146         page_address_t pg;
    147         frame_address_t fr;
    148 
    149         pg.address = t->page + (index << MMU_PAGE_WIDTH);
    150         fr.address = t->frame + (index << MMU_PAGE_WIDTH);
    151 
    152         tag.value = 0;
    153         tag.context = t->as->asid;
    154         tag.vpn = pg.vpn;
    155 
    156         dtlb_tag_access_write(tag.value);
    157 
     155void dtlb_pte_copy(pte_t *t, bool ro)
     156{
     157        tte_data_t data;
     158       
    158159        data.value = 0;
    159160        data.v = true;
    160         data.size = PAGESIZE_8K;
    161         data.pfn = fr.pfn;
    162         data.l = false;
     161        data.nfo = false;
     162        data.ra = (t->frame) >> FRAME_WIDTH;
     163        data.ie = false;
     164        data.e = false;
    163165        data.cp = t->c;
    164166#ifdef CONFIG_VIRT_IDX_DCACHE
    165167        data.cv = t->c;
    166 #endif /* CONFIG_VIRT_IDX_DCACHE */
    167         data.p = t->k;          /* p like privileged */
     168#endif
     169        data.p = t->k;
     170        data.x = false;
    168171        data.w = ro ? false : t->w;
    169         data.g = t->g;
    170 
    171         dtlb_data_in_write(data.value);
    172 }
    173 #endif
     172        data.size = PAGESIZE_8K;
     173       
     174        __hypercall_hyperfast(
     175                t->page, t->as->asid, data.value, MMU_FLAG_DTLB, 0, MMU_MAP_ADDR);
     176}
     177
    174178
    175179/** Copy PTE to ITLB.
     
    246250void fast_data_access_mmu_miss(uint64_t page_and_ctx, istate_t *istate)
    247251{
    248 #if 0
    249252        pte_t *t;
    250253        uintptr_t va = DMISS_ADDRESS(page_and_ctx);
     
    285288                }
    286289        }
    287 #endif
     290        asm volatile ("sethi 0x41941, %g0");
    288291}
    289292
    290293/** DTLB protection fault handler.
    291294 *
    292  * @param tag           Content of the TLB Tag Access register as it existed
    293  *                      when the trap happened. This is to prevent confusion
    294  *                      created by clobbered Tag Access register during a nested
    295  *                      DTLB miss.
     295 * @param page_and_ctx  A 64-bit value describing the fault. The most
     296 *                      significant 51 bits of the value contain the virtual
     297 *                      address which caused the fault truncated to the page
     298 *                      boundary. The least significant 13 bits of the value
     299 *                      contain the number of the context in which the fault
     300 *                      occurred.
    296301 * @param istate        Interrupted state saved on the stack.
    297302 */
    298303void fast_data_access_protection(uint64_t page_and_ctx, istate_t *istate)
    299304{
    300 #if 0
    301305        pte_t *t;
    302 
    303306        uintptr_t va = DMISS_ADDRESS(page_and_ctx);
    304307        uint16_t ctx = DMISS_CONTEXT(page_and_ctx);
     
    326329                 */             
    327330                page_table_unlock(AS, true);
    328                 if (as_page_fault(page_16k, PF_ACCESS_WRITE, istate) ==
    329                     AS_PF_FAULT) {
    330                         do_fast_data_access_protection_fault(istate, tag,
     331                if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
     332                        do_fast_data_access_protection_fault(istate, page_and_ctx,
    331333                            __func__);
    332334                }
    333335        }
    334 #endif
    335 }
     336}
     337
    336338
    337339/** Print TLB entry (for debugging purposes).
     
    357359}
    358360
    359 #if 0
    360361void do_fast_data_access_mmu_miss_fault(istate_t *istate,
    361362    uint64_t page_and_ctx, const char *str)
     
    366367        }
    367368        dump_istate(istate);
    368         printf("Faulting page: %p, ASID=%d.\n", va, tag.context);
    369         panic("%s.", str);
    370 }
    371 #endif
    372 
    373 #if 0
     369        printf("Faulting page: %p, ASID=%d\n", DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
     370        panic("%s\n", str);
     371}
     372
    374373void do_fast_data_access_protection_fault(istate_t *istate,
    375374    uint64_t page_and_ctx, const char *str)
     
    381380        printf("Faulting page: %p, ASID=%d\n", DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx));
    382381        dump_istate(istate);
    383         panic("%s.", str);
    384 }
    385 #endif
     382        panic("%s\n", str);
     383}
    386384
    387385/**
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