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Changeset 534bcdf in mainline


Ignore:
Timestamp:
2019-04-06T09:02:46Z (22 months ago)
Author:
Jakub Jermar <jakub@…>
Branches:
master
Children:
3daba42e
Parents:
fd67c9f
Message:

Always configure pic1 to start 8 IRQs after pic0

Location:
kernel
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/amd64/src/amd64.c

    rfd67c9f r534bcdf  
    121121                /* PIC */
    122122                i8259_init((i8259_t *) I8259_PIC0_BASE,
    123                     (i8259_t *) I8259_PIC1_BASE, IRQ_PIC1, IVT_IRQBASE,
    124                     IVT_IRQBASE + 8);
     123                    (i8259_t *) I8259_PIC1_BASE, IRQ_PIC1, IVT_IRQBASE);
    125124
    126125                /*
  • kernel/arch/ia32/src/ia32.c

    rfd67c9f r534bcdf  
    110110                /* PIC */
    111111                i8259_init((i8259_t *) I8259_PIC0_BASE,
    112                     (i8259_t *) I8259_PIC1_BASE, IRQ_PIC1, IVT_IRQBASE,
    113                     IVT_IRQBASE + 8);
     112                    (i8259_t *) I8259_PIC1_BASE, IRQ_PIC1, IVT_IRQBASE);
    114113
    115114                /*
  • kernel/arch/mips32/src/mach/malta/malta.c

    rfd67c9f r534bcdf  
    9999        irq_init(ISA_IRQ_COUNT, ISA_IRQ_COUNT);
    100100
    101         i8259_init((i8259_t *) PIC0_BASE, (i8259_t *) PIC1_BASE, 2, 0, 8);
     101        i8259_init((i8259_t *) PIC0_BASE, (i8259_t *) PIC1_BASE, 2, 0);
    102102
    103103        int_handler[INT_HW0] = malta_isa_irq_handler;
  • kernel/genarch/include/genarch/drivers/i8259/i8259.h

    rfd67c9f r534bcdf  
    6060} __attribute__((packed)) i8259_t;
    6161
    62 extern void i8259_init(i8259_t *, i8259_t *, inr_t, unsigned int, unsigned int);
     62extern void i8259_init(i8259_t *, i8259_t *, inr_t, unsigned int);
    6363extern void pic_enable_irqs(uint16_t);
    6464extern void pic_disable_irqs(uint16_t);
  • kernel/genarch/src/drivers/i8259/i8259.c

    rfd67c9f r534bcdf  
    4848
    4949void i8259_init(i8259_t *pic0, i8259_t *pic1, inr_t pic1_irq,
    50     unsigned int irq0_int, unsigned int irq8_int)
     50    unsigned int irq0_vec)
    5151{
    5252        saved_pic0 = pic0;
     
    5656        pio_write_8(&pic0->port1, PIC_ICW1 | PIC_ICW1_NEEDICW4);
    5757
    58         /* ICW2: IRQ 0 maps to INT irq0_int */
    59         pio_write_8(&pic0->port2, irq0_int);
     58        /* ICW2: IRQ 0 maps to interrupt vector address irq0_vec */
     59        pio_write_8(&pic0->port2, irq0_vec);
    6060
    6161        /* ICW3: pic1 using IRQ IRQ_PIC1 */
     
    6868        pio_write_8(&pic1->port1, PIC_ICW1 | PIC_ICW1_NEEDICW4);
    6969
    70         /* ICW2: IRQ 8 maps to INT irq8_int */
    71         pio_write_8(&pic1->port2, irq8_int);
     70        /* ICW2: IRQ 8 maps to interrupt vector address irq0_vec + 8 */
     71        pio_write_8(&pic1->port2, irq0_vec + PIC_IRQ_COUNT);
    7272
    7373        /* ICW3: pic1 is known as IRQ_PIC1 */
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