Changeset 5265eea4 in mainline for boot/arch/arm32/src/asm.S

Timestamp:

2015-10-28T18:17:27Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

77a194c, ff381a7

Parents:

0328987 (diff), 5783d10 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge various ARM fixes from lp:~jakub/helenos/arm

Fix GTA02 uspace/kernel memory corruption caused by wrong TLB
invalidation. ARM920T does not have a unified TLB, so it is necessary
to purge the instruction and data TLBs separately.

Fix RaspberryPi support. Make RaspberryPi use non-shared memory
(eliminating thus a weird special case for ARMv6) and invalidate the
entire D-cache before it is re-enabled in the kernel.

Make the CP15 cache-related macros non-ARMv7-centric for ARMv6-. Define
only macros that are supported by the given CPU/architecture (partially).

Be more careful and do not assume ARMv7 features. This relates to
enabling branch predictors, prefetch buffer and various control bits
in some registers.

File:

• boot/arch/arm32/src/asm.S (modified) (2 diffs)

boot/arch/arm32/src/asm.S

@@ -75 +75 @@
         bic     r4, r4, #(1 << CP15_C1_DC)
 
-        # Disable I-cache and Branche predictors.
+        # Disable I-cache and Branch predictors.
         bic     r4, r4, #(1 << CP15_C1_IC)
+#ifdef PROCESSOR_ARCH_armv6
         bic     r4, r4, #(1 << CP15_C1_BP)
+#endif
         
         mcr     p15, 0, r4, c1, c0, 0
 #endif
-
-
         
-        #Wait for the operations to complete
+        # Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         dsb
 #else
-        #cp15 dsb, r4 is ignored (should be zero)
+        # cp15 dsb, r4 is ignored (should be zero)
         mov r4, #0
         mcr p15, 0, r4, c7, c10, 4
@@ -98 +98 @@
         nop
 
-        #Wait for the operations to complete
+        # Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         isb
         nop
-#else
+#elif defined(PROCESSOR_ARCH_armv6)
         # cp15 isb
         mcr p15, 0, r4, c7, c5, 4