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Changeset 4d02595 in mainline


Ignore:
Timestamp:
2012-04-02T22:45:50Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
6b3ee0c5
Parents:
1bd99214
Message:

arm32, boot: Turn on caching and alignment, in addition to paging.

This should speed things up a little.

Location:
boot/arch/arm32
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/include/mm.h

    r1bd99214 r4d02595  
    5858        unsigned int bufferable : 1;
    5959        unsigned int cacheable : 1;
    60         unsigned int impl_specific : 1;
     60        unsigned int xn : 1;
    6161        unsigned int domain : 4;
    6262        unsigned int should_be_zero_1 : 1;
    63         unsigned int access_permission : 2;
    64         unsigned int should_be_zero_2 : 8;
     63        unsigned int access_permission_0 : 2;
     64        unsigned int tex : 3;
     65        unsigned int access_permission_1 : 2;
     66        unsigned int non_global : 1;
     67        unsigned int should_be_zero_2 : 1;
     68        unsigned int non_secure : 1;
    6569        unsigned int section_base_addr : 12;
    6670} __attribute__((packed)) pte_level0_section_t;
  • boot/arch/arm32/src/mm.c

    r1bd99214 r4d02595  
    5454{
    5555        pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
    56         pte->bufferable = 0;
     56        pte->bufferable = 1;
    5757        pte->cacheable = 0;
    58         pte->impl_specific = 0;
     58        pte->xn = 0;
    5959        pte->domain = 0;
    6060        pte->should_be_zero_1 = 0;
    61         pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
     61        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
     62        pte->tex = 0;
     63        pte->access_permission_1 = 0;
     64        pte->non_global = 0;
    6265        pte->should_be_zero_2 = 0;
     66        pte->non_secure = 0;
    6367        pte->section_base_addr = frame;
    6468}
     
    6771static void init_boot_pt(void)
    6872{
    69 /* BeagleBoard-xM (MD37x) memory starts at 2GB border,
    70  * thus mapping only lower 2GB is not not enough.
    71  * Map entire AS 1:1 instead and hope it works. */
    72 #ifdef MACHINE_beagleboardxm
    7373        const pfn_t split_page = PTL0_ENTRIES;
    74 #else
    75         const pfn_t split_page = 0x800;
    76 #endif
    7774        /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
    7875        pfn_t page;
     
    8481         * (upper 2 GB), physical addresses start from 0.
    8582         */
     83        /* BeagleBoard-xM (MD37x) memory starts at 2GB border,
     84         * thus mapping only lower 2GB is not not enough.
     85         * Map entire AS 1:1 instead and hope it works. */
    8686        for (page = split_page; page < PTL0_ENTRIES; page++)
     87#ifndef MACHINE_beagleboardxm
    8788                init_ptl0_section(&boot_pt[page], page - split_page);
     89#else
     90                init_ptl0_section(&boot_pt[page], page);
     91#endif
    8892       
    8993        asm volatile (
     
    106110                "mrc p15, 0, r0, c1, c0, 0\n"
    107111               
    108                 /* Mask to enable paging */
    109                 "ldr r1, =0x00000001\n"
     112                /* Mask to enable paging, alignment and caching */
     113                "ldr r1, =0x00000007\n"
    110114                "orr r0, r0, r1\n"
    111115               
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