Changeset 4ce90544 in mainline


Ignore:
Timestamp:
2011-05-30T21:48:13Z (13 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
df3c6f02, e8d5f9f
Parents:
0743493a (diff), 7b712b60 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge from lp:~jakub/helenos/ia64-revival.

Location:
kernel/arch/ia64
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia64/include/register.h

    r0743493a r4ce90544  
    6060#define PSR_CPL_SHIFT         32
    6161#define PSR_CPL_MASK_SHIFTED  3
     62
     63#define PSR_RI_SHIFT    41
     64#define PSR_RI_LEN      2
    6265
    6366#define PFM_MASK  (~0x3fffffffff)
  • kernel/arch/ia64/src/ivt.S

    r0743493a r4ce90544  
    5050#define R_KSTACK_BSP    r22     /* keep in sync with before_thread_runs_arch() */
    5151#define R_KSTACK        r23     /* keep in sync with before_thread_runs_arch() */
     52
     53/* Speculation vector handler */
     54.macro SPECULATION_VECTOR_HANDLER offs
     55    .org ivt + \offs
     56
     57    /* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
     58        mov r16 = pr
     59        mov r17 = cr.iim
     60        mov r18 = cr.iip
     61        mov r19 = cr.ipsr
     62        mov r20 = cr.isr ;;
     63       
     64    /* 2. Move IIP to IIPA. */
     65        mov cr.iipa = r18
     66       
     67    /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
     68        shl r17 = r17, 43 ;;    /* shift bit 20 to bit 63 */
     69        shr r17 = r17, 39 ;;    /* signed shift right to bit 24 */
     70        add r18 = r18, r17 ;;
     71        mov cr.iip = r18
     72       
     73    /* 4. Set IPSR.ri to 0. */
     74        dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
     75        mov cr.ipsr = r19
     76       
     77    /* 5. Check whether IPSR.tb or IPSR.ss is set. */
     78
     79        /* TODO:
     80         * Implement this when Taken Branch and Single Step traps can occur.
     81         */
     82   
     83    /* 6. Restore predicates and return from interruption. */
     84        mov pr = r16 ;;
     85        rfi
     86.endm
    5287
    5388/** Heavyweight interrupt handler
     
    541576        HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
    542577        HEAVYWEIGHT_HANDLER 0x5600
    543         HEAVYWEIGHT_HANDLER 0x5700
     578        SPECULATION_VECTOR_HANDLER 0x5700
    544579        HEAVYWEIGHT_HANDLER 0x5800
    545580        HEAVYWEIGHT_HANDLER 0x5900
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