Changeset 4cdcd2b in mainline for kernel/genarch/include/genarch/drivers/am335x/irc.h
- Timestamp:
- 2013-09-10T13:01:57Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- e8d6ce2
- Parents:
- 5b08d750 (diff), 3c9646b (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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links above to see all the changes relative to each parent. - File:
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- 1 edited
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kernel/genarch/include/genarch/drivers/am335x/irc.h
r5b08d750 r4cdcd2b 38 38 #define KERN_AM335x_IRQC_H_ 39 39 40 #define AM335x_IRC_BASE_ADDRESS 0x4820000041 #define AM335x_IRC_SIZE 409640 #define AM335x_IRC_BASE_ADDRESS 0x48200000 41 #define AM335x_IRC_SIZE 4096 42 42 43 #define AM335x_IRC_IRQ_COUNT 128 43 #define AM335x_IRC_IRQ_COUNT 128 44 #define AM335x_IRC_IRQ_GROUPS_COUNT 4 44 45 45 #include <typedefs.h> 46 #define OMAP_IRC_IRQ_COUNT AM335x_IRC_IRQ_COUNT 47 #define OMAP_IRC_IRQ_GROUPS_COUNT AM335x_IRC_IRQ_GROUPS_COUNT 46 48 47 typedef struct { 48 const ioport32_t revision; 49 #define AM335x_IRC_REV_MASK 0xFF 50 51 const uint8_t padd0[12]; 52 53 /* This register controls the various parameters 54 * of the OCP interface. 55 */ 56 ioport32_t sysconfig; 57 #define AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) 58 #define AM335x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) 59 60 /* This register provides status information about the module */ 61 const ioport32_t sysstatus; 62 #define AM335x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) 63 64 const uint8_t padd1[40]; 65 66 /* This register supplies the currently active IRQ interrupt number */ 67 ioport32_t sir_irq; 68 #define AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK 0x7F 69 #define AM335x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 70 71 /* This register supplies the currently active FIQ interrupt number */ 72 const ioport32_t sir_fiq; 73 #define AM335x_IRC_FIQ_IRQ_ACTIVEFIQ_MASK 0x7F 74 #define AM335x_IRC_FIQ_IRQ_SPURIOUSFIQFLAG_MASK 0xFFFFFFF8 75 76 /* This register contains the new interrupt agreement bits */ 77 ioport32_t control; 78 #define AM335x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) 79 #define AM335x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) 80 81 /* This register controls protection of the other registers. 82 * This register can only be accessed in priviledged mode, regardless 83 * of the current value of the protection bit. 84 */ 85 ioport32_t protection; 86 #define AM335x_IRC_PROTECTION_FLAG (1 << 0) 87 88 /* This register controls the clock auto-idle for the functional 89 * clock and the input synchronizers. 90 */ 91 ioport32_t idle; 92 #define AM335x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) 93 #define AM335x_IRC_IDLE_TURBO_FLAG (1 << 1) 94 95 const uint8_t padd2[12]; 96 97 /* This register supplies the currently active IRQ priority level */ 98 const ioport32_t irq_priority; 99 #define AM335x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK 0x7F 100 #define AM335x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 101 102 /* This register supplies the currently active FIQ priority level */ 103 const ioport32_t fiq_priority; 104 #define AM335x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK 0x7F 105 #define AM335x_IRC_FIQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8 106 107 /* This register sets the priority threshold */ 108 ioport32_t threshold; 109 #define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK 0xFF 110 #define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED 0x00 111 #define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED 0xFF 112 113 const uint8_t padd[20]; 114 115 struct { 116 /* Raw interrupt input status before masking */ 117 const ioport32_t itr; 118 119 /* Interrupt mask */ 120 ioport32_t mir; 121 122 /* This register is used to clear the interrupt mask bits, 123 * Write 1 clears the mask bit to 0. 124 */ 125 ioport32_t mir_clear; 126 127 /* This register is used to set the interrupt mask bits, 128 * Write 1 sets the mask bit to 1. 129 */ 130 ioport32_t mir_set; 131 132 /* This register is used to set the software interrupt bits, 133 * it is also used to read the current active software 134 * interrupts. 135 * Write 1 sets the software interrups bits to 1. 136 */ 137 ioport32_t isr_set; 138 139 /* This register is used to clear the software interrups bits. 140 * Write 1 clears the software interrupt bits to 0. 141 */ 142 ioport32_t isr_clear; 143 144 /* This register contains the IRQ status after masking. */ 145 const ioport32_t pending_irq; 146 147 /* This register contains the FIQ status after masking. */ 148 const ioport32_t pending_fiq; 149 } interrupts[4]; 150 151 /* These registers contain the priority for the interrups and 152 * the FIQ/IRQ steering. 153 */ 154 ioport32_t ilr[AM335x_IRC_IRQ_COUNT]; 155 /* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */ 156 #define AM335x_IRC_ILR_FIQNIRQ_FLAG (1 << 0) 157 #define AM335x_IRC_ILR_PRIORITY_MASK 0x3F 158 #define AM335x_IRC_ILR_PRIORITY_SHIFT 2 159 160 } am335x_irc_regs_t; 161 162 static inline void am335x_irc_init(am335x_irc_regs_t *regs) 163 { 164 int i; 165 166 /* Initialization sequence */ 167 168 /* 1 - Program the SYSCONFIG register: if necessary, enable the 169 * autogating by setting the AUTOIDLE bit. 170 */ 171 regs->sysconfig &= ~AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG; 172 173 /* 2 - Program the IDLE register: if necessary, disable functional 174 * clock autogating or enable synchronizer autogating by setting 175 * the FUNCIDLE bit or the TURBO bit accordingly. 176 */ 177 regs->idle &= ~AM335x_IRC_IDLE_FUNCIDLE_FLAG; 178 regs->idle &= ~AM335x_IRC_IDLE_TURBO_FLAG; 179 180 /* 3 - Program ILRm register for each interrupt line: Assign a 181 * priority level and set the FIQNIRQ bit for an FIQ interrupt 182 * (by default, interrupts are mapped to IRQ and 183 * priority is 0 (highest). 184 */ 185 186 for (i = 0; i < AM335x_IRC_IRQ_COUNT; ++i) 187 regs->ilr[i] = 0; 188 189 /* 4 - Program the MIRn register: Enable interrupts (by default, 190 * all interrupt lines are masked). 191 */ 192 for (i = 0; i < 4; ++i) 193 regs->interrupts[i].mir_set = 0xFFFFFFFF; 194 } 195 196 /** Get the currently active IRQ interrupt number 197 * 198 * @param regs Pointer to the irc memory mapped registers 199 * 200 * @return The active IRQ interrupt number 201 */ 202 static inline unsigned am335x_irc_inum_get(am335x_irc_regs_t *regs) 203 { 204 return regs->sir_irq & AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; 205 } 206 207 /** Reset IRQ output and enable new IRQ generation 208 * 209 * @param regs Pointer to the irc memory mapped registers 210 */ 211 static inline void am335x_irc_irq_ack(am335x_irc_regs_t *regs) 212 { 213 regs->control = AM335x_IRC_CONTROL_NEWIRQAGR_FLAG; 214 } 215 216 /** Reset FIQ output and enable new FIQ generation 217 * 218 * @param regs Pointer to the irc memory mapped registers 219 */ 220 static inline void am335x_irc_fiq_ack(am335x_irc_regs_t *regs) 221 { 222 regs->control = AM335x_IRC_CONTROL_NEWFIQAGR_FLAG; 223 } 224 225 /** Clear an interrupt mask bit 226 * 227 * @param regs Pointer to the irc memory mapped registers 228 * @param inum The interrupt to be enabled 229 */ 230 static inline void am335x_irc_enable(am335x_irc_regs_t *regs, unsigned inum) 231 { 232 ASSERT(inum < AM335x_IRC_IRQ_COUNT); 233 const unsigned set = inum / 32; 234 const unsigned pos = inum % 32; 235 regs->interrupts[set].mir_clear = (1 << pos); 236 } 237 238 /** Set an interrupt mask bit 239 * 240 * @param regs Pointer to the irc memory mapped registers 241 * @param inum The interrupt to be disabled 242 */ 243 static inline void am335x_irc_disable(am335x_irc_regs_t *regs, unsigned inum) 244 { 245 ASSERT(inum < AM335x_IRC_IRQ_COUNT); 246 const unsigned set = inum / 32; 247 const unsigned pos = inum % 32; 248 regs->interrupts[set].mir_set = (1 << pos); 249 } 49 #include <genarch/drivers/omap/irc.h> 250 50 251 51 #endif
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