Fork us on GitHub Follow us on Facebook Follow us on Twitter

Changeset 4b28c70 in mainline


Ignore:
Timestamp:
2013-01-19T22:59:00Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
3fa509b
Parents:
c3213bb
Message:

arm32: CLIDR is armv7 only.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/cpu/cpu.c

    rc3213bb r4b28c70  
    225225unsigned dcache_levels(void)
    226226{
     227        unsigned levels = 0;
     228#ifdef PROCESSOR_ARCH_armv7_a
    227229        const uint32_t val = CLIDR_read();
    228         unsigned levels = 0;
    229230        for (unsigned i = 1; i <= 7; ++i) {
    230231                const unsigned ctype = CLIDR_CACHE(i, val);
     
    238239                }
    239240        }
     241#endif
    240242        return levels;
    241243}
Note: See TracChangeset for help on using the changeset viewer.