Changeset 49e6c6b4 in mainline for kernel/arch/ia32/src/smp/apic.c

Timestamp:

2012-06-30T23:54:42Z (12 years ago)

Author:

Adam Hraska <adam.hraska+hos@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2ee1ccc

Parents:

1f092d9

Message:

ipi: Added support for unicast IPI on amd64, ia32.

File:

• kernel/arch/ia32/src/smp/apic.c (modified) (3 diffs)

kernel/arch/ia32/src/smp/apic.c

@@ -259 +259 @@
 }
 
+static void ipi_wait_for_idle(void)
+{
+        icr_t icr;
+        
+        /* Wait for the destination cpu to accept the previous ipi. */
+        do {
+                icr.lo = l_apic[ICRlo];
+        } while (icr.delivs != DELIVS_IDLE);
+}
+
+/** Send one CPU an IPI vector.
+ *
+ * @param apicid Physical APIC ID of the destination CPU.
+ * @param vector Interrupt vector to be sent.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+int l_apic_send_custom_ipi(uint8_t apicid, uint8_t vector)
+{
+        icr_t icr;
+
+        /* Wait for a destination cpu to accept our previous ipi. */
+        ipi_wait_for_idle();
+        
+        icr.lo = l_apic[ICRlo];
+        icr.hi = l_apic[ICRhi];
+        
+        icr.delmod = DELMOD_FIXED;
+        icr.destmod = DESTMOD_PHYS;
+        icr.level = LEVEL_ASSERT;
+        icr.shorthand = SHORTHAND_NONE;
+        icr.trigger_mode = TRIGMOD_LEVEL;
+        icr.vector = vector;
+        icr.dest = apicid;
+
+        /* Send the IPI by writing to l_apic[ICRlo]. */
+        l_apic[ICRhi] = icr.hi;
+        l_apic[ICRlo] = icr.lo;
+        
+#ifdef CONFIG_DEBUG
+        icr.lo = l_apic[ICRlo];
+        if (icr.delivs == DELIVS_PENDING) {
+                printf("IPI is pending.\n");
+        }
+#endif
+        
+        return apic_poll_errors();
+}
+
 /** Send all CPUs excluding CPU IPI vector.
  *
@@ -269 +318 @@
 {
         icr_t icr;
+
+        /* Wait for a destination cpu to accept our previous ipi. */
+        ipi_wait_for_idle();
         
         icr.lo = l_apic[ICRlo];
@@ -466 +518 @@
         dfr.model = MODEL_FLAT;
         l_apic[DFR] = dfr.value;
+        
+        if (CPU->arch.id != l_apic_id()) {
+#ifdef CONFIG_DEBUG
+                printf("lapic error: LAPIC ID (%" PRIu8 ") and hw ID assigned by BSP"
+                        " (%u) differ. Correcting to LAPIC ID.\n", l_apic_id(), 
+                        CPU->arch.id);
+#endif
+                CPU->arch.id = l_apic_id();
+        }
+        
 }