Changeset 49e6c6b4 in mainline

Timestamp:

2012-06-30T23:54:42Z (12 years ago)

Author:

Adam Hraska <adam.hraska+hos@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2ee1ccc

Parents:

1f092d9

Message:

ipi: Added support for unicast IPI on amd64, ia32.

Location:

kernel

Files:

• arch/amd64/include/cpu.h (modified) (1 diff)
• arch/amd64/src/amd64.c (modified) (1 diff)
• arch/amd64/src/cpu/cpu.c (modified) (1 diff)
• arch/ia32/include/cpu.h (modified) (1 diff)
• arch/ia32/include/smp/apic.h (modified) (1 diff)
• arch/ia32/src/cpu/cpu.c (modified) (1 diff)
• arch/ia32/src/ia32.c (modified) (1 diff)
• arch/ia32/src/smp/apic.c (modified) (3 diffs)
• arch/ia32/src/smp/smp.c (modified) (3 diffs)
• generic/src/main/main.c (modified) (1 diff)

kernel/arch/amd64/include/cpu.h

@@ -73 +73 @@
         tss_t *tss;
         
+        unsigned int id; /** CPU's local, ie physical, APIC ID. */
+        
         size_t iomapver_copy;  /** Copy of TASK's I/O Permission bitmap generation count. */
 } cpu_arch_t;

kernel/arch/amd64/src/amd64.c

@@ -171 +171 @@
 }
 
-void arch_post_cpu_init()
+void arch_post_cpu_init(void)
 {
 #ifdef CONFIG_SMP

kernel/arch/amd64/src/cpu/cpu.c

@@ -158 +158 @@
 void cpu_print_report(cpu_t* m)
 {
-        printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
+        printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
             m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
-            m->arch.stepping, m->frequency_mhz);
+            m->arch.stepping, m->arch.id, m->frequency_mhz);
 }
 

kernel/arch/ia32/include/cpu.h

@@ -60 +60 @@
         unsigned int stepping;
         cpuid_feature_info fi;
+        
+        unsigned int id; /** CPU's local, ie physical, APIC ID. */
 
         tss_t *tss;

kernel/arch/ia32/include/smp/apic.h

@@ -353 +353 @@
 extern void l_apic_init(void);
 extern void l_apic_eoi(void);
+extern int l_apic_send_custom_ipi(uint8_t, uint8_t);
 extern int l_apic_broadcast_custom_ipi(uint8_t);
 extern int l_apic_send_init_ipi(uint8_t);

kernel/arch/ia32/src/cpu/cpu.c

@@ -160 +160 @@
 void cpu_print_report(cpu_t* cpu)
 {
-        printf("cpu%u: (%s family=%u model=%u stepping=%u) %" PRIu16 " MHz\n",
-                cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
-                cpu->arch.model, cpu->arch.stepping, cpu->frequency_mhz);
+        printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16 
+                " MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
+                cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
 }
 

kernel/arch/ia32/src/ia32.c

@@ -125 +125 @@
 }
 
-void arch_post_cpu_init()
+void arch_post_cpu_init(void)
 {
 #ifdef CONFIG_SMP

kernel/arch/ia32/src/smp/apic.c

@@ -259 +259 @@
 }
 
+static void ipi_wait_for_idle(void)
+{
+        icr_t icr;
+        
+        /* Wait for the destination cpu to accept the previous ipi. */
+        do {
+                icr.lo = l_apic[ICRlo];
+        } while (icr.delivs != DELIVS_IDLE);
+}
+
+/** Send one CPU an IPI vector.
+ *
+ * @param apicid Physical APIC ID of the destination CPU.
+ * @param vector Interrupt vector to be sent.
+ *
+ * @return 0 on failure, 1 on success.
+ */
+int l_apic_send_custom_ipi(uint8_t apicid, uint8_t vector)
+{
+        icr_t icr;
+
+        /* Wait for a destination cpu to accept our previous ipi. */
+        ipi_wait_for_idle();
+        
+        icr.lo = l_apic[ICRlo];
+        icr.hi = l_apic[ICRhi];
+        
+        icr.delmod = DELMOD_FIXED;
+        icr.destmod = DESTMOD_PHYS;
+        icr.level = LEVEL_ASSERT;
+        icr.shorthand = SHORTHAND_NONE;
+        icr.trigger_mode = TRIGMOD_LEVEL;
+        icr.vector = vector;
+        icr.dest = apicid;
+
+        /* Send the IPI by writing to l_apic[ICRlo]. */
+        l_apic[ICRhi] = icr.hi;
+        l_apic[ICRlo] = icr.lo;
+        
+#ifdef CONFIG_DEBUG
+        icr.lo = l_apic[ICRlo];
+        if (icr.delivs == DELIVS_PENDING) {
+                printf("IPI is pending.\n");
+        }
+#endif
+        
+        return apic_poll_errors();
+}
+
 /** Send all CPUs excluding CPU IPI vector.
  *
@@ -269 +318 @@
 {
         icr_t icr;
+
+        /* Wait for a destination cpu to accept our previous ipi. */
+        ipi_wait_for_idle();
         
         icr.lo = l_apic[ICRlo];
@@ -466 +518 @@
         dfr.model = MODEL_FLAT;
         l_apic[DFR] = dfr.value;
+        
+        if (CPU->arch.id != l_apic_id()) {
+#ifdef CONFIG_DEBUG
+                printf("lapic error: LAPIC ID (%" PRIu8 ") and hw ID assigned by BSP"
+                        " (%u) differ. Correcting to LAPIC ID.\n", l_apic_id(), 
+                        CPU->arch.id);
+#endif
+                CPU->arch.id = l_apic_id();
+        }
+        
 }
 

kernel/arch/ia32/src/smp/smp.c

@@ -55 +55 @@
 #include <memstr.h>
 #include <arch/drivers/i8259.h>
+#include <cpu.h>
 
 #ifdef CONFIG_SMP
@@ -77 +78 @@
                 io_apic = (uint32_t *) km_map((uintptr_t) io_apic, PAGE_SIZE,
                     PAGE_WRITE | PAGE_NOT_CACHEABLE);
+        }
+}
+
+static void cpu_arch_id_init(void)
+{
+        ASSERT(ops != NULL);
+        ASSERT(cpus != NULL);
+        
+        for (unsigned int i = 0; i < config.cpu_count; ++i) {
+                cpus[i].arch.id = ops->cpu_apic_id(i);
         }
 }
@@ -92 +103 @@
         
         ASSERT(ops != NULL);
+
+        /*
+         * SMP initialized, cpus array allocated. Assign each CPU its 
+         * physical APIC ID.
+         */
+        cpu_arch_id_init();
         
         /*

kernel/generic/src/main/main.c

@@ -244 +244 @@
         
         cpu_init();
-        
         calibrate_delay_loop();
+        arch_post_cpu_init();
+
         clock_counter_init();
         timeout_init();