Changeset 467f0c0 in mainline for kernel/arch/arm32/src/fpu_context.c

Timestamp:

2013-01-10T20:53:07Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1f271d9

Parents:

6a6ebde

Message:

arm32: Only check cpacr on armv7. Earlier versions do not support the reg.

Add note about user level synchs to barrier.h

File:

• kernel/arch/arm32/src/fpu_context.c (modified) (4 diffs)

kernel/arch/arm32/src/fpu_context.c

@@ -125 +125 @@
 static int fpu_have_coprocessor_access()
 {
+/* The register containing the information (CPACR) is not available on armv6-
+ * rely on user decision to use CONFIG_FPU.
+ */
+#ifndef PROCESSOR_armv7_a
+        return 1;
+#endif
         uint32_t cpacr;
         asm volatile ("MRC p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
@@ -149 +155 @@
 static void fpu_enable_coprocessor_access()
 {
+/* The register containing the information (CPACR) is not available on armv6-
+ * rely on user decision to use CONFIG_FPU.
+ */
+#ifndef PROCESSOR_armv7_a
+        return;
+#endif
         uint32_t cpr;
         asm volatile("MRC p15, 0, %0, c1, c1, 0" : "=r" (cpr)::);
@@ -169 +181 @@
         uint32_t cpacr;
         asm volatile ("mrc p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+        printf("CPACR before: %x\n", cpacr);
         /* FPU needs access to coprocessor 10 and 11.
          * Moreover, they need to have same access enabled */
@@ -174 +187 @@
         cpacr |= CPACR_CP11_USER_ACCESS;
         asm volatile ("mcr p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+        printf("CPACR after: %x\n", cpacr);
 
 #ifdef MACHINE_beagleboardxm