Changes in / [216cb85:45d5f86] in mainline
- Files:
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- 2 deleted
- 8 edited
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kernel/arch/arm32/Makefile.inc
r216cb85 r45d5f86 61 61 arch/$(KARCH)/src/mm/page.c \ 62 62 arch/$(KARCH)/src/mm/tlb.c \ 63 arch/$(KARCH)/src/mm/page_fault.c \ 64 arch/$(KARCH)/src/ras.c 63 arch/$(KARCH)/src/mm/page_fault.c 65 64 66 65 ifeq ($(MACHINE),testarm) -
kernel/arch/arm32/src/arm32.c
r216cb85 r45d5f86 48 48 #include <macros.h> 49 49 #include <string.h> 50 #include <arch/ras.h>51 50 52 51 #ifdef MACHINE_testarm … … 89 88 exception_init(); 90 89 interrupt_init(); 91 92 /* Initialize Restartable Atomic Sequences support. */93 ras_init();94 90 95 91 machine_output_init(); -
kernel/arch/arm32/src/exc_handler.S
r216cb85 r45d5f86 148 148 mov r0, #0 149 149 mov r1, r13 150 bl ras_check150 bl exc_dispatch 151 151 LOAD_REGS_FROM_STACK 152 152 … … 156 156 mov r0, #5 157 157 mov r1, r13 158 bl ras_check158 bl exc_dispatch 159 159 LOAD_REGS_FROM_STACK 160 160 … … 164 164 mov r0, #6 165 165 mov r1, r13 166 bl ras_check166 bl exc_dispatch 167 167 LOAD_REGS_FROM_STACK 168 168 … … 171 171 mov r0, #1 172 172 mov r1, r13 173 bl ras_check173 bl exc_dispatch 174 174 LOAD_REGS_FROM_STACK 175 175 … … 179 179 mov r0, #3 180 180 mov r1, r13 181 bl ras_check181 bl exc_dispatch 182 182 LOAD_REGS_FROM_STACK 183 183 … … 187 187 mov r0, #4 188 188 mov r1, r13 189 bl ras_check189 bl exc_dispatch 190 190 LOAD_REGS_FROM_STACK 191 191 … … 195 195 mov r0, #2 196 196 mov r1, r13 197 bl ras_check197 bl exc_dispatch 198 198 LOAD_REGS_FROM_STACK 199 199 -
kernel/arch/arm32/src/userspace.c
r216cb85 r45d5f86 35 35 36 36 #include <userspace.h> 37 #include <arch/ras.h>38 37 39 38 /** Struct for holding all general purpose registers. … … 75 74 ustate.r1 = 0; 76 75 77 /* pass the RAS page address in %r2 */78 ustate.r2 = (uintptr_t) ras_page;79 80 76 /* clear other registers */ 81 ustate.r 3 = ustate.r4 = ustate.r5 = ustate.r6 = ustate.r7=82 ustate.r 8 = ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 =83 ustate. lr = 0;77 ustate.r2 = ustate.r3 = ustate.r4 = ustate.r5 = 78 ustate.r6 = ustate.r7 = ustate.r8 = ustate.r9 = ustate.r10 = 79 ustate.r11 = ustate.r12 = ustate.lr = 0; 84 80 85 81 /* set user stack */ -
uspace/lib/libc/arch/arm32/include/atomic.h
r216cb85 r45d5f86 37 37 #define LIBC_arm32_ATOMIC_H_ 38 38 39 #define LIBC_ARCH_ATOMIC_H_ 40 #define CAS 39 #include <bool.h> 41 40 42 #include <atomicdflt.h> 43 #include <bool.h> 44 #include <sys/types.h> 41 typedef struct atomic { 42 volatile long count; 43 } atomic_t; 45 44 46 extern uintptr_t *ras_page; 45 static inline void atomic_set(atomic_t *val, long i) 46 { 47 val->count = i; 48 } 49 50 static inline long atomic_get(atomic_t *val) 51 { 52 return val->count; 53 } 47 54 48 55 static inline bool cas(atomic_t *val, long ov, long nv) 49 56 { 50 long ret = 0; 51 52 /* 53 * The following instructions between labels 1 and 2 constitute a 54 * Restartable Atomic Seqeunce. Should the sequence be non-atomic, 55 * the kernel will restart it. 56 */ 57 asm volatile ( 58 "1:\n" 59 " adr %[ret], 1b\n" 60 " str %[ret], %[rp0]\n" 61 " adr %[ret], 2f\n" 62 " str %[ret], %[rp1]\n" 63 " ldr %[ret], %[addr]\n" 64 " cmp %[ret], %[ov]\n" 65 " streq %[nv], %[addr]\n" 66 "2:\n" 67 " moveq %[ret], #1\n" 68 " movne %[ret], #0\n" 69 : [ret] "+&r" (ret), 70 [rp0] "=m" (ras_page[0]), 71 [rp1] "=m" (ras_page[1]), 72 [addr] "+m" (val->count) 73 : [ov] "r" (ov), 74 [nv] "r" (nv) 75 : "memory" 76 ); 77 78 ras_page[0] = 0; 79 asm volatile ("" ::: "memory"); 80 ras_page[1] = 0xffffffff; 81 82 return (bool) ret; 57 /* FIXME: is not atomic */ 58 if (val->count == ov) { 59 val->count = nv; 60 return true; 61 } 62 return false; 83 63 } 84 64 … … 92 72 static inline long atomic_add(atomic_t *val, int i) 93 73 { 94 long ret = 0; 74 int ret; 75 volatile long * mem = &(val->count); 95 76 96 /* 97 * The following instructions between labels 1 and 2 constitute a 98 * Restartable Atomic Seqeunce. Should the sequence be non-atomic, 99 * the kernel will restart it. 100 */ 77 /* FIXME: is not atomic, is broken */ 101 78 asm volatile ( 102 "1:\n" 103 " adr %[ret], 1b\n" 104 " str %[ret], %[rp0]\n" 105 " adr %[ret], 2f\n" 106 " str %[ret], %[rp1]\n" 107 " ldr %[ret], %[addr]\n" 108 " add %[ret], %[ret], %[imm]\n" 109 " str %[ret], %[addr]\n" 110 "2:\n" 111 : [ret] "+&r" (ret), 112 [rp0] "=m" (ras_page[0]), 113 [rp1] "=m" (ras_page[1]), 114 [addr] "+m" (val->count) 115 : [imm] "r" (i) 79 "1:\n" 80 "ldr r2, [%1]\n" 81 "add r3, r2, %2\n" 82 "str r3, %0\n" 83 "swp r3, r3, [%1]\n" 84 "cmp r3, r2\n" 85 "bne 1b\n" 86 87 : "=m" (ret) 88 : "r" (mem), "r" (i) 89 : "r3", "r2" 116 90 ); 117 118 ras_page[0] = 0;119 asm volatile ("" ::: "memory");120 ras_page[1] = 0xffffffff;121 91 122 92 return ret; -
uspace/lib/libc/arch/arm32/src/entry.s
r216cb85 r45d5f86 36 36 # 37 37 # r1 contains the PCB pointer 38 # r2 contains the RAS page address39 38 # 40 39 __entry: 41 # Store the RAS page address into the ras_page variable42 ldr r0, =ras_page43 str r2, [r0]44 45 40 # Pass pcb_ptr to __main as the first argument (in r0) 46 41 mov r0, r1 … … 48 43 49 44 bl __exit 50 51 .data52 53 .global ras_page54 ras_page:55 .long 056 -
uspace/lib/libc/include/atomicdflt.h
r216cb85 r45d5f86 56 56 } 57 57 58 #ifndef CAS59 58 static inline bool cas(atomic_t *val, long ov, long nv) 60 59 { 61 60 return __sync_bool_compare_and_swap(&val->count, ov, nv); 62 61 } 63 #endif64 62 65 63 #endif -
uspace/srv/loader/arch/arm32/arm32.s
r216cb85 r45d5f86 36 36 # Jump to a program entry point 37 37 program_run: 38 # load ras_page address to r239 ldr r2, =ras_page40 ldr r2, [r2]41 38 # pcb is passed to the entry point in r1 (where it already is) 42 39 mov r15, r0
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