Changeset 3fa509b in mainline for kernel/arch/arm32/include/cp15.h
- Timestamp:
- 2013-01-19T23:59:25Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9eec7bc
- Parents:
- 4b28c70
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/include/cp15.h
r4b28c70 r3fa509b 416 416 CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4); 417 417 418 /* c9 are reserved */ 418 /* c9 are performance monitoring resgisters */ 419 enum { 420 PMCR_IMP_MASK = 0xff, 421 PMCR_IMP_SHIFT = 24, 422 PMCR_IDCODE_MASK = 0xff, 423 PMCR_IDCODE_SHIFT = 16, 424 PMCR_EVENT_NUM_MASK = 0x1f, 425 PMCR_EVENT_NUM_SHIFT = 11, 426 PMCR_DP_FLAG = 1 << 5, 427 PMCR_X_FLAG = 1 << 4, 428 PMCR_D_FLAG = 1 << 3, 429 PMCR_C_FLAG = 1 << 2, 430 PMCR_P_FLAG = 1 << 1, 431 PMCR_E_FLAG = 1 << 0, 432 }; 433 CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0); 434 CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0); 435 enum { 436 PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31, 437 #define PMCNTENSET_COUNTER_EN_FLAG(c) (1 << c) 438 }; 439 CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1); 440 CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1); 441 CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0); 442 CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0); 443 419 444 420 445 /*c10 has tons of reserved too */
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