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Changeset 3fa509b in mainline


Ignore:
Timestamp:
2013-01-19T23:59:25Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
9eec7bc
Parents:
4b28c70
Message:

arm32, armv7: Add reading of performance cycles counter.

Fix comment about WFE.

Location:
kernel/arch/arm32
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/asm.h

    r4b28c70 r3fa509b  
    4343#include <trace.h>
    4444
    45 /** No such instruction on old ARM to sleep CPU.
     45/** CPU specific way to sleep cpu.
    4646 *
    4747 * ARMv7 introduced wait for event and wait for interrupt (wfe/wfi).
  • kernel/arch/arm32/include/cp15.h

    r4b28c70 r3fa509b  
    416416CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
    417417
    418 /* c9 are reserved */
     418/* c9 are performance monitoring resgisters */
     419enum {
     420        PMCR_IMP_MASK = 0xff,
     421        PMCR_IMP_SHIFT = 24,
     422        PMCR_IDCODE_MASK = 0xff,
     423        PMCR_IDCODE_SHIFT = 16,
     424        PMCR_EVENT_NUM_MASK = 0x1f,
     425        PMCR_EVENT_NUM_SHIFT = 11,
     426        PMCR_DP_FLAG = 1 << 5,
     427        PMCR_X_FLAG = 1 << 4,
     428        PMCR_D_FLAG = 1 << 3,
     429        PMCR_C_FLAG = 1 << 2,
     430        PMCR_P_FLAG = 1 << 1,
     431        PMCR_E_FLAG = 1 << 0,
     432};
     433CONTROL_REG_GEN_READ(PMCR, c9, 0, c12, 0);
     434CONTROL_REG_GEN_WRITE(PMCR, c9, 0, c12, 0);
     435enum {
     436        PMCNTENSET_CYCLE_COUNTER_EN_FLAG = 1 << 31,
     437#define PMCNTENSET_COUNTER_EN_FLAG(c)   (1 << c)
     438};
     439CONTROL_REG_GEN_READ(PMCNTENSET, c9, 0, c12, 1);
     440CONTROL_REG_GEN_WRITE(PMCNTENSET, c9, 0, c12, 1);
     441CONTROL_REG_GEN_READ(PMCCNTR, c9, 0, c13, 0);
     442CONTROL_REG_GEN_WRITE(PMCCNTR, c9, 0, c13, 0);
     443
    419444
    420445/*c10 has tons of reserved too */
  • kernel/arch/arm32/include/cycle.h

    r4b28c70 r3fa509b  
    3838
    3939#include <trace.h>
     40#include <arch/cp15.h>
    4041
    4142/** Return count of CPU cycles.
     
    4849NO_TRACE static inline uint64_t get_cycle(void)
    4950{
     51#ifdef PROCESSOR_ARCH_armv7_a
     52        if ((ID_PFR1_read() & ID_PFR1_GEN_TIMER_EXT_MASK) ==
     53            ID_PFR1_GEN_TIMER_EXT) {
     54            uint32_t low = 0, high = 0;
     55            asm volatile( "MRRC p15, 0, %[low], %[high], c14": [low]"=r"(low), [high]"=r"(high));
     56           return ((uint64_t)high << 32) | low;
     57        } else {
     58                return PMCCNTR_read();
     59        }
     60#endif
    5061        return 0;
    5162}
  • kernel/arch/arm32/src/cpu/cpu.c

    r4b28c70 r3fa509b  
    168168        fpu_setup();
    169169#endif
     170
     171#ifdef PROCESSOR_ARCH_armv7_a
     172        PMCR_write(PMCR_read() | PMCR_E_FLAG);
     173        PMCNTENSET_write(PMCNTENSET_CYCLE_COUNTER_EN_FLAG);
     174#endif
    170175}
    171176
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