Changeset 3f3afb9 in mainline for uspace/drv/ohci/ohci_regs.h
- Timestamp:
- 2011-04-11T20:38:37Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 1324ff3, a39cfb8
- Parents:
- 58226b4 (diff), d91645ab (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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uspace/drv/ohci/ohci_regs.h
r58226b4 r3f3afb9 84 84 /** Interupt enable/disable, reads give the same value, writing causes 85 85 * enable/disable */ 86 volatile uint32_t inter upt_enable;86 volatile uint32_t interrupt_enable; 87 87 volatile uint32_t interrupt_disable; 88 88 #define I_SO (1 << 0) /* Scheduling overrun */ … … 100 100 #define HCCA_PTR_MASK 0xffffff00 /* HCCA is 256B aligned */ 101 101 102 /** Currently executed period endpoint */103 const volatile uint32_t period _current;102 /** Currently executed periodic endpoint */ 103 const volatile uint32_t periodic_current; 104 104 105 105 /** The first control endpoint */ … … 120 120 /** Frame time and max packet size for all transfers */ 121 121 volatile uint32_t fm_interval; 122 #define FMI_FI_MASK (0x 1fff) /* Frame interval in bit times (should be 11999)*/122 #define FMI_FI_MASK (0x3fff) /* Frame interval in bit times (should be 11999)*/ 123 123 #define FMI_FI_SHIFT (0) 124 124 #define FMI_FSMPS_MASK (0x7fff) /* Full speed max packet size */ … … 138 138 /** Remaining bit time in frame to start periodic transfers */ 139 139 volatile uint32_t periodic_start; 140 #define PS_PS_MASK (0x 1fff) /* bit time when periodic get priority (0x3e67) */140 #define PS_PS_MASK (0x3fff) /* bit time when periodic get priority (0x3e67) */ 141 141 142 142 /** Threshold for starting LS transaction */
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