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Changeset 3d9d948 in mainline


Ignore:
Timestamp:
2010-07-27T20:13:05Z (11 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master
Children:
1720cf9
Parents:
a9b5b5f
Message:

Operate S3C24xx UART in FIFO mode.

Files:
2 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/src/drivers/s3c24xx_uart/s3c24xx_uart.c

    ra9b5b5f r3d9d948  
    5151#define S3C24XX_UTRSTAT_RDATA           0x1
    5252
     53#define S3C24XX_UFSTAT_TX_FULL          0x4000
     54#define S3C24XX_UFSTAT_RX_FULL          0x0040
     55#define S3C24XX_UFSTAT_RX_COUNT         0x002f
     56
    5357static void s3c24xx_uart_sendb(outdev_t *dev, uint8_t byte)
    5458{
     
    5660            (s3c24xx_uart_t *) dev->data;
    5761
    58         /* Wait for transmitter to be empty. */
    59         while ((pio_read_32(&uart->io->utrstat) & S3C24XX_UTRSTAT_TX_EMPTY) == 0)
     62        /* Wait for space becoming available in Tx FIFO. */
     63        while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
    6064                ;
    6165
     
    8589        s3c24xx_uart_t *uart = irq->instance;
    8690
    87         if ((pio_read_32(&uart->io->utrstat) & S3C24XX_UTRSTAT_RDATA) != 0) {
     91        while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
    8892                uint32_t data = pio_read_32(&uart->io->urxh);
     93                pio_read_32(&uart->io->uerstat);
    8994                indev_push_character(uart->indev, data & 0xff);
    9095        }
     
    123128        uart->irq.instance = uart;
    124129
    125         /* Disable FIFO */
    126         pio_write_32(&uart->io->ufcon,
    127             pio_read_32(&uart->io->ufcon) & ~0x01);
     130        /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
     131        pio_write_32(&uart->io->ufcon, 0x01);
    128132
    129133        /* Set RX interrupt to pulse mode */
  • uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c

    ra9b5b5f r3d9d948  
    5757#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
    5858#define S3C24XX_UTRSTAT_RDATA           0x1
     59
     60/* Bits in UFSTAT register */
     61#define S3C24XX_UFSTAT_TX_FULL          0x4000
     62#define S3C24XX_UFSTAT_RX_FULL          0x0040
     63#define S3C24XX_UFSTAT_RX_COUNT         0x002f
    5964
    6065static irq_cmd_t uart_irq_cmds[] = {
     
    155160        (void) iid; (void) call;
    156161
    157         if ((pio_read_32(&uart->io->utrstat) & S3C24XX_UTRSTAT_RDATA) != 0) {
     162        while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_RX_COUNT) != 0) {
    158163                uint32_t data = pio_read_32(&uart->io->urxh) & 0xff;
     164                pio_read_32(&uart->io->uerstat);
    159165
    160166                if (uart->client_phone != -1) {
     
    206212static void s3c24xx_uart_sendb(s3c24xx_uart_t *uart, uint8_t byte)
    207213{
    208         /* Wait for transmitter to be empty. */
    209         while ((pio_read_32(&uart->io->utrstat) & S3C24XX_UTRSTAT_TX_EMPTY) == 0)
     214        /* Wait for space becoming available in Tx FIFO. */
     215        while ((pio_read_32(&uart->io->ufstat) & S3C24XX_UFSTAT_TX_FULL) != 0)
    210216                ;
    211217
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