Changeset 3500f75 in mainline for kernel/arch/ppc32/include/asm.h
- Timestamp:
- 2010-05-21T22:50:45Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7c8e1e1
- Parents:
- 339249f
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ppc32/include/asm.h
r339249f r3500f75 38 38 #include <typedefs.h> 39 39 #include <config.h> 40 #include <arch/cpu.h> 41 42 static inline uint32_t msr_read(void) 43 { 44 uint32_t msr; 45 46 asm volatile ( 47 "mfmsr %[msr]\n" 48 : [msr] "=r" (msr) 49 ); 50 51 return msr; 52 } 53 54 static inline void msr_write(uint32_t msr) 55 { 56 asm volatile ( 57 "mtmsr %[msr]\n" 58 :: [msr] "r" (msr) 59 ); 60 } 40 61 41 62 /** Enable interrupts. … … 45 66 * 46 67 * @return Old interrupt priority level. 68 * 47 69 */ 48 70 static inline ipl_t interrupts_enable(void) 49 71 { 50 ipl_t v; 51 ipl_t tmp; 52 53 asm volatile ( 54 "mfmsr %0\n" 55 "mfmsr %1\n" 56 "ori %1, %1, 1 << 15\n" 57 "mtmsr %1\n" 58 : "=r" (v), "=r" (tmp) 59 ); 60 return v; 72 ipl_t ipl = msr_read(); 73 msr_write(ipl | MSR_EE); 74 return ipl; 61 75 } 62 76 … … 67 81 * 68 82 * @return Old interrupt priority level. 83 * 69 84 */ 70 85 static inline ipl_t interrupts_disable(void) 71 86 { 72 ipl_t v; 73 ipl_t tmp; 74 75 asm volatile ( 76 "mfmsr %0\n" 77 "mfmsr %1\n" 78 "rlwinm %1, %1, 0, 17, 15\n" 79 "mtmsr %1\n" 80 : "=r" (v), "=r" (tmp) 81 ); 82 return v; 87 ipl_t ipl = msr_read(); 88 msr_write(ipl & (~MSR_EE)); 89 return ipl; 83 90 } 84 91 … … 88 95 * 89 96 * @param ipl Saved interrupt priority level. 97 * 90 98 */ 91 99 static inline void interrupts_restore(ipl_t ipl) 92 100 { 93 ipl_t tmp; 94 95 asm volatile ( 96 "mfmsr %1\n" 97 "rlwimi %0, %1, 0, 17, 15\n" 98 "cmpw 0, %0, %1\n" 99 "beq 0f\n" 100 "mtmsr %0\n" 101 "0:\n" 102 : "=r" (ipl), "=r" (tmp) 103 : "0" (ipl) 104 : "cr0" 105 ); 101 msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE)); 106 102 } 107 103 … … 111 107 * 112 108 * @return Current interrupt priority level. 109 * 113 110 */ 114 111 static inline ipl_t interrupts_read(void) 115 112 { 116 ipl_t v; 117 118 asm volatile ( 119 "mfmsr %0\n" 120 : "=r" (v) 121 ); 122 return v; 113 return msr_read(); 114 } 115 116 /** Check whether interrupts are disabled. 117 * 118 * @return True if interrupts are disabled. 119 * 120 */ 121 static inline bool interrupts_disabled(void) 122 { 123 return ((msr_read() & MSR_EE) == 0); 123 124 } 124 125 … … 128 129 * The stack is assumed to be STACK_SIZE bytes long. 129 130 * The stack must start on page boundary. 131 * 130 132 */ 131 133 static inline uintptr_t get_stack_base(void) 132 134 { 133 uintptr_t v;135 uintptr_t base; 134 136 135 137 asm volatile ( 136 "and % 0, %%sp, %1\n"137 : "=r" (v)138 : "r" (~(STACK_SIZE - 1))138 "and %[base], %%sp, %[mask]\n" 139 : [base] "=r" (base) 140 : [mask] "r" (~(STACK_SIZE - 1)) 139 141 ); 140 return v; 142 143 return base; 141 144 } 142 145
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