Changeset 3412e844 in mainline


Ignore:
Timestamp:
2012-11-24T02:28:47Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
f1e496a
Parents:
6e634d6
Message:

arm32: Implement basic support for FPU context switching.

Lazy fpu context switching is not supported, yet.

Location:
kernel/arch/arm32
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/Makefile.inc

    r6e634d6 r3412e844  
    3434
    3535GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
     36
     37ifeq ($(CONFIG_FPU),y)
     38# This is necessary to allow vmsr insn and fpexc manipulation
     39GCC_CFLAGS += -mfloat-abi=hard
     40endif
    3641
    3742BITS = 32
  • kernel/arch/arm32/include/fpu_context.h

    r6e634d6 r3412e844  
    4141#include <typedefs.h>
    4242
    43 #define FPU_CONTEXT_ALIGN    0
     43#define FPU_CONTEXT_ALIGN    8
    4444
     45/* ARM Architecture reference manual, p B-1529.
     46 * We don't enable EX bit so max 32 64bit regs are stored (+2 control regs)
     47 */
    4548typedef struct {
     49        uint32_t fpuscr;
     50        uint32_t fpuexc;
     51        uint32_t s[64];
    4652} fpu_context_t;
    4753
  • kernel/arch/arm32/src/cpu/cpu.c

    r6e634d6 r3412e844  
    3838#include <arch.h>
    3939#include <print.h>
     40#include <fpu_context.h>
    4041
    4142/** Number of indexes left out in the #imp_data array */
     
    138139}
    139140
     141void fpu_init(void)
     142{
     143        //TODO: Identify FPU unit
     144        //and set correct functions to save/restore ctx
     145}
     146
     147void fpu_enable(void)
     148{
     149        /* Enable FPU instructions */
     150        asm volatile (
     151                "ldr r1, =0x40000000\n"
     152                "vmsr fpexc, r1\n"
     153                ::: "r1"
     154        );
     155}
     156
     157void fpu_disable(void)
     158{
     159        /* Disable FPU instructions */
     160        asm volatile (
     161                "ldr r1, =0x00000000\n"
     162                "vmsr fpexc, r1\n"
     163                ::: "r1"
     164        );
     165}
     166
     167void fpu_context_save(fpu_context_t *ctx)
     168{
     169        // TODO check and complete. What about fpexc?
     170        asm volatile (
     171                "vmrs r1, fpscr\n"
     172//              "vmrs r2, fpexc\n"
     173                "stm %0, {r1, r2}\n"
     174                "vstm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
     175                ::"r" (ctx): "r1","r2","memory"
     176        );
     177}
     178
     179void fpu_context_restore(fpu_context_t *ctx)
     180{
     181        // TODO check and complete. What about fpexc?
     182        asm volatile (
     183                "ldm %0, {r1, r2}\n"
     184                "vmsr fpscr, r1\n"
     185//              "vmsr fpexc, r2\n"
     186                "vldm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
     187                ::"r" (ctx): "r1","r2"
     188        );
     189}
     190
    140191/** Retrieves processor identification and stores it to #CPU.arch */
    141192void cpu_identify(void)
  • kernel/arch/arm32/src/dummy.S

    r6e634d6 r3412e844  
    3232.global asm_delay_loop
    3333
    34 .global fpu_context_restore
    35 .global fpu_context_save
    36 .global fpu_enable
    37 .global fpu_init
    38 
    3934.global sys_tls_set
    4035.global dummy
     
    4641        mov     pc, lr
    4742
    48 fpu_context_restore:
    49         mov     pc, lr
    50    
    51 fpu_context_save:
    52         mov     pc, lr
    53    
    54 fpu_enable:
    55         mov     pc, lr
    56 
    57 fpu_init:
    58         mov     pc, lr
    59    
    6043# not used on ARM
    6144sys_tls_set:
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