Changeset 32fb6bce in mainline for uspace/drv/bus/usb/uhci/hc.c
- Timestamp:
- 2017-12-18T22:50:21Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7f70d1c
- Parents:
- 1ea0bbf
- git-author:
- Ondřej Hlavatý <aearsis@…> (2017-12-18 22:04:50)
- git-committer:
- Ondřej Hlavatý <aearsis@…> (2017-12-18 22:50:21)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/uhci/hc.c
r1ea0bbf r32fb6bce 95 95 96 96 static void hc_init_hw(const hc_t *instance); 97 static int hc_init_mem_structures(hc_t *instance, hc d_t *);97 static int hc_init_mem_structures(hc_t *instance, hc_device_t *); 98 98 static int hc_init_transfer_lists(hc_t *instance); 99 99 … … 107 107 * @return Error code. 108 108 */ 109 int uhci_hc_gen_irq_code(irq_code_t *code, hcd_t *hcd, const hw_res_list_parsed_t *hw_res)109 int hc_gen_irq_code(irq_code_t *code, hc_device_t *hcd, const hw_res_list_parsed_t *hw_res) 110 110 { 111 111 assert(code); … … 156 156 * - resume from suspend state (not implemented) 157 157 */ 158 void uhci_hc_interrupt(hcd_t *hcd, uint32_t status) 159 { 160 assert(hcd); 161 hc_t *instance = hcd_get_driver_data(hcd); 162 assert(instance); 158 static void hc_interrupt(bus_t *bus, uint32_t status) 159 { 160 hc_t *instance = bus_to_hc(bus); 161 163 162 /* Lower 2 bits are transaction error and transaction complete */ 164 163 if (status & (UHCI_STATUS_INTERRUPT | UHCI_STATUS_ERROR_INTERRUPT)) { … … 199 198 } else { 200 199 usb_log_fatal("Too many UHCI hardware failures!.\n"); 201 hc_ fini(instance);200 hc_gone(&instance->base); 202 201 } 203 202 } … … 215 214 * interrupt fibrils. 216 215 */ 217 int hc_ init(hc_t *instance, hcd_t *hcd, const hw_res_list_parsed_t *hw_res)218 { 219 assert(instance);216 int hc_add(hc_device_t *hcd, const hw_res_list_parsed_t *hw_res) 217 { 218 hc_t *instance = hcd_to_hc(hcd); 220 219 assert(hw_res); 221 220 if (hw_res->io_ranges.count != 1 || … … 249 248 } 250 249 251 void hc_start(hc_t *instance) 252 { 250 int hc_start(hc_device_t *hcd) 251 { 252 hc_t *instance = hcd_to_hc(hcd); 253 253 hc_init_hw(instance); 254 254 (void)hc_debug_checker; 255 255 256 uhci_rh_init(&instance->rh, instance->registers->ports, "uhci");256 return uhci_rh_init(&instance->rh, instance->registers->ports, "uhci"); 257 257 } 258 258 … … 261 261 * @param[in] instance Host controller structure to use. 262 262 */ 263 void hc_fini(hc_t *instance)263 int hc_gone(hc_device_t *instance) 264 264 { 265 265 assert(instance); 266 266 //TODO Implement 267 return ENOTSUP; 267 268 } 268 269 … … 294 295 pio_write_32(®isters->flbaseadd, pa); 295 296 296 if (instance-> hw_interrupts) {297 if (instance->base.irq_cap >= 0) { 297 298 /* Enable all interrupts, but resume interrupt */ 298 299 pio_write_16(&instance->registers->usbintr, … … 320 321 } 321 322 323 static int hc_status(bus_t *, uint32_t *); 324 static int hc_schedule(usb_transfer_batch_t *); 325 322 326 static const bus_ops_t uhci_bus_ops = { 323 327 .parent = &usb2_bus_ops, 324 328 329 .interrupt = hc_interrupt, 330 .status = hc_status, 331 325 332 .endpoint_count_bw = bandwidth_count_usb11, 326 333 .batch_create = create_transfer_batch, 334 .batch_schedule = hc_schedule, 327 335 .batch_destroy = destroy_transfer_batch, 328 336 }; … … 338 346 * - frame list page (needs to be one UHCI hw accessible 4K page) 339 347 */ 340 int hc_init_mem_structures(hc_t *instance, hc d_t *hcd)348 int hc_init_mem_structures(hc_t *instance, hc_device_t *hcd) 341 349 { 342 350 int err; 343 351 assert(instance); 344 352 345 if ((err = usb2_bus_init(&instance->bus, hcd,BANDWIDTH_AVAILABLE_USB11)))353 if ((err = usb2_bus_init(&instance->bus, BANDWIDTH_AVAILABLE_USB11))) 346 354 return err; 347 355 348 356 bus_t *bus = (bus_t *) &instance->bus; 349 357 bus->ops = &uhci_bus_ops; 358 359 hc_device_setup(&instance->base, bus); 350 360 351 361 /* Init USB frame list page */ … … 438 448 } 439 449 440 int uhci_hc_status(hcd_t *hcd, uint32_t *status)441 { 442 assert(hcd);450 static int hc_status(bus_t *bus, uint32_t *status) 451 { 452 hc_t *instance = bus_to_hc(bus); 443 453 assert(status); 444 hc_t *instance = hcd_get_driver_data(hcd);445 assert(instance);446 454 447 455 *status = 0; … … 462 470 * Checks for bandwidth availability and appends the batch to the proper queue. 463 471 */ 464 int uhci_hc_schedule(hcd_t *hcd, usb_transfer_batch_t *batch) 465 { 466 assert(hcd); 467 hc_t *instance = hcd_get_driver_data(hcd); 468 assert(instance); 472 static int hc_schedule(usb_transfer_batch_t *batch) 473 { 474 hc_t *instance = bus_to_hc(endpoint_get_bus(batch->ep)); 469 475 assert(batch); 470 476
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