Index: kernel/arch/ia64/include/asm.h
===================================================================
--- kernel/arch/ia64/include/asm.h	(revision a1d89adda9a437fbce84276519b5bcb94321f87d)
+++ kernel/arch/ia64/include/asm.h	(revision 309ede113b6ed9f76d3b2f6cd08386f96836a161)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
@@ -41,14 +41,17 @@
 #include <arch/register.h>
 
-#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
+#define IA64_IOSPACE_ADDRESS  0xE001000000000000ULL
 
 static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	*((ioport8_t *)(IA64_IOSPACE_ADDRESS +
+	
+	*((ioport8_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
-
-	asm volatile ("mf\n" ::: "memory");
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
 }
 
@@ -56,9 +59,12 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	*((ioport16_t *)(IA64_IOSPACE_ADDRESS +
+	
+	*((ioport16_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
-
-	asm volatile ("mf\n" ::: "memory");
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
 }
 
@@ -66,9 +72,12 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	*((ioport32_t *)(IA64_IOSPACE_ADDRESS +
+	
+	*((ioport32_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
-
-	asm volatile ("mf\n" ::: "memory");
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
 }
 
@@ -76,8 +85,11 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	asm volatile ("mf\n" ::: "memory");
-
-	return *((ioport8_t *)(IA64_IOSPACE_ADDRESS +
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+	
+	return *((ioport8_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
@@ -86,8 +98,11 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	asm volatile ("mf\n" ::: "memory");
-
-	return *((ioport16_t *)(IA64_IOSPACE_ADDRESS +
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+	
+	return *((ioport16_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
@@ -96,8 +111,11 @@
 {
 	uintptr_t prt = (uintptr_t) port;
-
-	asm volatile ("mf\n" ::: "memory");
-
-	return *((ioport32_t *)(IA64_IOSPACE_ADDRESS +
+	
+	asm volatile (
+		"mf\n"
+		::: "memory"
+	);
+	
+	return *((ioport32_t *) (IA64_IOSPACE_ADDRESS +
 	    ((prt & 0xfff) | ((prt >> 2) << 12))));
 }
@@ -112,13 +130,24 @@
 {
 	uint64_t v;
-
-	//I'm not sure why but this code bad inlines in scheduler, 
-	//so THE shifts about 16B and causes kernel panic
-	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
-	//return v;
-	
-	//this code have the same meaning but inlines well
-	asm volatile ("mov %0 = r12" : "=r" (v)  );
-	return v & (~(STACK_SIZE-1));
+	
+	/* I'm not sure why but this code bad inlines in scheduler,
+	   so THE shifts about 16B and causes kernel panic
+	   
+	   asm volatile (
+	       "and %[value] = %[mask], r12"
+	       : [value] "=r" (v)
+	       : [mask] "r" (~(STACK_SIZE - 1))
+	   );
+	   return v;
+	   
+	   This code have the same meaning but inlines well.
+	*/
+	
+	asm volatile (
+		"mov %[value] = r12"
+		: [value] "=r" (v)
+	);
+	
+	return (v & (~(STACK_SIZE - 1)));
 }
 
@@ -131,5 +160,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = psr\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = psr\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -144,5 +176,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.iva\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -155,5 +190,8 @@
 static inline void iva_write(uint64_t v)
 {
-	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.iva = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -167,5 +205,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.ivr\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -176,5 +217,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr64\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr64\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -188,5 +232,8 @@
 static inline void itc_write(uint64_t v)
 {
-	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
+	asm volatile (
+		"mov ar.itc = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -199,5 +246,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = ar.itc\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -210,5 +260,8 @@
 static inline void itm_write(uint64_t v)
 {
-	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.itm = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -221,5 +274,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.itm\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -234,5 +290,8 @@
 	uint64_t v;
 	
-	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
+	asm volatile (
+		"mov %[value] = cr.itv\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -245,5 +304,8 @@
 static inline void itv_write(uint64_t v)
 {
-	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.itv = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -254,5 +316,8 @@
 static inline void eoi_write(uint64_t v)
 {
-	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.eoi = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -264,6 +329,9 @@
 {
 	uint64_t v;
-
-	asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
+	
+	asm volatile (
+		"mov %[value] = cr.tpr\n"
+		: [value] "=r" (v)
+	);
 	
 	return v;
@@ -276,5 +344,8 @@
 static inline void tpr_write(uint64_t v)
 {
-	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
+	asm volatile (
+		"mov cr.tpr = %[value]\n"
+		:: [value] "r" (v)
+	);
 }
 
@@ -291,8 +362,8 @@
 	
 	asm volatile (
-		"mov %0 = psr\n"
-		"rsm %1\n"
-		: "=r" (v)
-		: "i" (PSR_I_MASK)
+		"mov %[value] = psr\n"
+		"rsm %[mask]\n"
+		: [value] "=r" (v)
+		: [mask] "i" (PSR_I_MASK)
 	);
 	
@@ -312,10 +383,10 @@
 	
 	asm volatile (
-		"mov %0 = psr\n"
-		"ssm %1\n"
+		"mov %[value] = psr\n"
+		"ssm %[mask]\n"
 		";;\n"
 		"srlz.d\n"
-		: "=r" (v)
-		: "i" (PSR_I_MASK)
+		: [value] "=r" (v)
+		: [mask] "i" (PSR_I_MASK)
 	);
 	
@@ -349,5 +420,8 @@
 static inline void pk_disable(void)
 {
-	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
+	asm volatile (
+		"rsm %[mask]\n"
+		:: [mask] "i" (PSR_PK_MASK)
+	);
 }
 
