Changeset 2bf4936 in mainline for kernel/arch/sparc64/include/trap/mmu.h

Timestamp:

2009-04-14T15:50:56Z (15 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade

Children:

47a6708

Parents:

577b531

Message:

On sparc64, do fast indentity mapping only for physical memory.
For addresses above physical memory, such as I/O devices,
fall through to the C miss handler and map the memory noncacheably.
Replace deprecated Bicc instructions with proper Bcc instructions.

File:

• kernel/arch/sparc64/include/trap/mmu.h (modified) (2 diffs)

kernel/arch/sparc64/include/trap/mmu.h

@@ -104 +104 @@
          */
 0:
-        mov VA_DMMU_TAG_ACCESS, %g1
-        ldxa [%g1] ASI_DMMU, %g1                        ! read the faulting Context and VPN
+        sethi %hi(fast_data_access_mmu_miss_data_hi), %g7
+        wr %g0, ASI_DMMU, %asi
+        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
         set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
         andcc %g1, %g2, %g3                             ! get Context
-        bnz 0f                                          ! Context is non-zero
+        bnz %xcc, 0f                                    ! Context is non-zero
         andncc %g1, %g2, %g3                            ! get page address into %g3
-        bz 0f                                           ! page address is zero
+        bz  %xcc, 0f                                    ! page address is zero
+        ldx [%g7 + %lo(end_of_identity)], %g4
+        cmp %g3, %g4
+        bgeu %xcc, 0f
 
-        sethi %hi(kernel_8k_tlb_data_template), %g2
-        ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
+        ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2
         or %g3, %g2, %g2
         stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
@@ -139 +142 @@
          * This is necessary to survive nested DTLB misses.
          */     
-        mov VA_DMMU_TAG_ACCESS, %g2
-        ldxa [%g2] ASI_DMMU, %g2
+        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
 
         /*